JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.9 General Purpose LDOs (LDO3, LDO4)

over operating free-air temperature range (unless otherwise noted)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
8.1.1 VIN Input Voltage (LDO-mode) (1) LDO-mode, maximum VVSYS 2.2 5.5 V
8.1.2 VIN Input Voltage (LSW-mode) (1) LSW-mode, maximum VVSYS 2.2 5.5 V
8.1.3 VOUT
LDO Output Voltage configurable Range

 VIN = 2.2V to 5.5V, maximum VVSYS 1.2 3.3 V
8.1.4 VOUT_STEP Output voltage Steps 1.2V ≤ VOUT ≤ 3.3V 50 mV
8.1.5 VDROPOUT Dropout Voltage VINmin ≤ VIN ≤ VINmax, IOUT = IOUTmax 150 300 mV
8.1.6 VOUT_DC_ACCURACY Total DC accuracy including DC load and line regulation for all valid output voltages LDO-mode, VIN - VOUT > 300 mV –1% 1%
8.1.7 RBYPASS Bypass resistance in LSW-mode VIN = 3.3V, IOUT = 100mA, Loadswitch-mode enabled 1 Ω
8.2.1 VLOAD_TRANSIENT Transient load regulation, ΔVOUT VIN = 3.3V, VOUT = 1.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1µs, COUT = 2.2µF –25 25 mV
8.2.2 VLINE_TRANSIENT Transient line regulation,
ΔVOUT / VOUT		 On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10µs –25 25 mV
8.2.3 NOISERMS RMS Noise LDO-mode, f=100Hz to 100KHz, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 15 µVRMS
8.2.4 PSRR1KHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 71 db
8.2.5 PSRR10KHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 64 db
8.2.6 PSRR100KHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 61 db
8.2.7 PSRR1MHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 26 db
8.3.1 IOUT Output Current 300 mA
8.3.2 ICURRENT_LIMIT Short Circuit Current Limit VIN = 3.6V, VOUT = 0V, Tested under a pulsed load condition 400 900 mA
8.3.3 IIN_RUSH LDO inrush current LDO- or LSW-mode, VIN = 3.3V and then LDO is enabled, COUT = 4µF, IOUT = 0 mA or 300mA 650 mA
8.3.4 RDISCHARGE Active only when converter is disabled 120 250 400 Ω
8.3.5a IQ_ACTIVE Quiescent Current in ACTIVE state at 25°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LDO-mode,
TJ = 25°C		 25 30 µA
8.3.5b IQ_ACTIVE Quiescent Current in ACTIVE state -40°C to 125°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LDO-mode,
TJ = -40°C to 125°C		 25 40 µA
8.3.5b IQ_ACTIVE
Quiescent Current in ACTIVE state -40°C to 150°C
 		 VVSYS = VIN = 3.3 V, IOUT = 0 mA,
Applies to LDO-mode,
TJ = -40°C to 150°C		 25 40 µA
8.3.5c IQ_ACTIVE Quiescent Current in ACTIVE state at 25°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LSW-mode,
TJ = 25°C		 60 112 µA
8.3.5d IQ_ACTIVE Quiescent Current in ACTIVE state -40°C to 125°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LSW-mode,
TJ = -40°C to 125°C		 70 145 µA
8.3.5d IQ_ACTIVE
Quiescent Current in ACTIVE state -40°C to 150°C
 		 VVSYS = VIN = 3.3 V, IOUT = 0 mA,
Applies to LSW-mode,
TJ = -40°C to 150°C		 70 145 µA
8.4.1 CIN Input Filtering Capacitance (2) 2.2 4.7 µF
8.4.2 COUT Output Filtering Capacitance (2) Connected from VLDOx to GND, LDO-mode 1.6 2.2 4 µF
8.4.3a COUT_TOTAL_FAST Total Capacitance at Output (Local + POL), fast ramp-time (3) 1 MHz < f < 10 MHz, impedance between output and point-of-load maximum 6nH 15 µF
8.4.3b COUT_TOTAL_SLOW Total Capacitance at Output (Local + POL), slow ramp-time (3) 1 MHz < f < 10 MHz, impedance between output and point-of-load maximum 6nH 30 µF
8.4.4 CESR Filtering capacitor ESR max 1MHz to 10MHz 10 20 mΩ
Timing Requirements
8.5.1a tRAMP_FAST Ramp Time fast Measured from enable to 98% of target value, LDO-mode, measured when enabled individually, assuming no residual voltage 660 µs
8.5.1b tRAMP_SLOW Ramp Time slow Measured from enable to 98% of target value, LDO-mode, measured when enabled individually, assuming no residual voltage 2.3 ms
8.5.2a tRAMP_SLEW_FAST Ramp Up Slew Rate fast LDO- or LSW-mode, measured from 0.5V to target value 25 mV/µs
8.5.2b tRAMP_SLEW_SLOW Ramp Up Slew Rate slow LDO- or LSW-mode, measured from 0.5V to target value 9 mV/µs
(1) PVIN_LDOx must not exceed VSYS
(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators.
(3) Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable