JAJSPM1C March   2011  – November 2023 TPS40170

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  LDO Linear Regulators and Enable
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
        1. 6.3.2.1 Equations for Programming the Input UVLO:
      3. 6.3.3  Oscillator and Voltage Feed-Forward
        1. 6.3.3.1 Calculating the Timing Resistance (RRT)
      4. 6.3.4  Overcurrent Protection and Short-Circuit Protection (OCP and SCP)
      5. 6.3.5  Soft-Start and Fault-Logic
        1. 6.3.5.1 Soft Start During Overcurrent Fault
        2. 6.3.5.2 Equations for Soft Start and Restart Time
      6. 6.3.6  Overtemperature Fault
      7. 6.3.7  Tracking
      8. 6.3.8  Adaptive Drivers
      9. 6.3.9  Start-Up into Pre-Biased Output
      10. 6.3.10 Power Good (PGOOD)
      11. 6.3.11 PGND and AGND
    4. 6.4 Device Functional Modes
      1. 6.4.1 Frequency Synchronization
      2. 6.4.2 Operation Near Minimum VIN (VVIN ≤ 4.5 V)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Bootstrap Resistor
      2. 7.1.2 SW Node Snubber Capacitor
      3. 7.1.3 Input Resistor
      4. 7.1.4 LDRV Gate Capacitor
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design with WEBENCH® Tools
        2. 7.2.2.2  List of Materials
        3. 7.2.2.3  Select a Switching Frequency
        4. 7.2.2.4  Inductor Selection (L1)
        5. 7.2.2.5  Output Capacitor Selection (C9)
        6. 7.2.2.6  Peak Current Rating of Inductor
        7. 7.2.2.7  Input Capacitor Selection (C1, C6)
        8. 7.2.2.8  MOSFET Switch Selection (Q1, Q2)
        9. 7.2.2.9  Timing Resistor (R7)
        10. 7.2.2.10 UVLO Programming Resistors (R2, R6)
        11. 7.2.2.11 Boot-Strap Capacitor (C7)
        12. 7.2.2.12 VIN Bypass Capacitor (C18)
        13. 7.2.2.13 VBP Bypass Capacitor (C19)
        14. 7.2.2.14 VDD Bypass Capacitor (C16)
        15. 7.2.2.15 SS Timing Capacitor (C15)
        16. 7.2.2.16 ILIM Resistor (R9, C17)
        17. 7.2.2.17 SCP Multiplier Selection (R5)
        18. 7.2.2.18 Feedback Divider (R10, R11)
        19. 7.2.2.19 Compensation: (R4, R13, C13, C14, C21)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design with WEBENCH® Tools
      3. 8.1.3 Related Devices
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Unless otherwise stated, these specifications apply for –40ºC ≤ TJ ≤ 125ºC, VVIN=12 V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VVIN Input voltage range 4.5 60 V
ISD Shutdown current VENABLE < 100 mV 1 2.5 µA
IQ Operating current, drivers not switching VENABLE ≥ 2 V, fSW = 300 kHz 4.5 mA
ENABLE
VDIS ENABLE pin voltage to disable the device 100 mV
VEN ENABLE pin voltage to enable the device 600
IENABLE ENABLE pin source current 300 nA
8-V AND 3.3-V REGULATORS
VBP 8 V regulator output voltage VENABLE ≥ 2 V, 8.2 V < VIN ≤ 60 V,
0 mA < IIN < 20 mA		 7.8 8.0 8.3 V
VDO 8 V regulator dropout voltage,
VIN-BP		 4.5 < VIN ≤ 8.2 V, VEN ≥ 2.0 V,
IIN = 10 mA		 110 200 mV
VVDD 3.3 V regulator output voltage VENABLE ≥ 2 V, 4.5 V < VIN ≤ 60 V,
0 mA < IIN < 5 mA 		3.22 3.30 3.42 V
FIXED AND PROGRAMMABLE UVLO
VUVLO Programmable UVLO ON voltage (at UVLO pin) VENABLE ≥ 2 V 878 900 919 mV
IUVLO Hysteresis current out of UVLO pin VENABLE ≥ 2 V , UVLO pin > VUVLO 4.06 5.00 6.20 µA
VBP(ON) VBP turn-on voltage VENABLE ≥ 2 V, UVLO pin > VUVLO 3.85 4.40 V
VBP(OFF) VBP turn-off voltage 3.60 4.05
VBP(HYS) VBP UVLO Hysteresis voltage 180 400 mV
REFERENCE
VREF Reference voltage (+ input of the error amplifier) TJ = 25°C, 4.5 V < VIN ≤ 60 V 594 600 606 mV
–40°C ≤ TJ ≤ 125ºC, 4.5 V < VIN ≤ 60 V 591 600 609
OSCILLATOR
fSW Switching frequency Range (typical) 100 600 kHz
RRT = 100 kΩ, 4.5 V <VIN ≤ 60 V 90 100 110
RRT = 31.6 kΩ, 4.5 V <VIN ≤ 60 V 270 300 330
RRT = 14.3 kΩ, 4.5 V <VIN ≤ 60 V 540 600 660
VVALLEY Valley voltage 0.7 1 1.2 V
KPWM(1) PWM Gain (VIN / VRAMP) 4.5 V < VIN ≤ 60 V 14 15 16 V/V
PWM AND DUTY CYCLE
tON(min)(1) Minimum controlled pulse VIN = 4.5 V, fSW = 300 kHz 100 150 ns
VIN = 12 V, fSW = 300 kHz 75 100
VIN = 60 V, fSW = 300 kHz 50 80
tOFF(max)(1) Minimum OFF time VIN = 12 V, fSW = 300 kHz 170 250
DMAX(1) Maximum duty cycle fSW = 100 kHz, 4.5 V < VIN ≤ 60 V 95%
FSW = 300 kHz, 4.5 V < VIN ≤ 60 V 91%
fSW = 600 kHz, 4.5 V < VIN ≤ 60 V 82%
ERROR AMPLIFIER
GBWP(1) Gain bandwidth product 7 10 13 MHz
AOL(1) Open-loop gain 80 90 95 dB
IIB Input bias current 100 nA
IEAOP Output source current VFB = 0 V 2 mA
IEAOM Output sink current VFB = 1 V 2
PROGRAMMABLE SOFT-START
ISS(source,start) Soft-start source current at VSS < 0.5 V VSS = 0.25 V 42 52 62 µA
ISS(source,normal) Soft-start source current at VSS > 0.5 V VSS = 1.5 V 9.3 11.6 13.9
ISS(sink) Soft-start sink current VSS = 1.5 V 0.77 1.05 1.33
VSS(fltH) SS pin HIGH voltage during fault (OC or thermal) reset timing 2.38 2.50 2.61 V
VSS(fltL) SS pin LOW voltage during fault (OC or thermal) reset timing 235 300 375 mV
VSS(steady_state) SS pin voltage during steady-state 3.25 3.30 3.50 V
VSS(offst) Initial offset voltage from SS pin to error amplifier input 525 650 775 mV
TRACKING
VTRK(ctrl)(1) Range of TRK which overrides VREF 4.5 V < VIN ≤ 60 V 0 600 mV
SYNCHRONIZATION (PRIMARY/SECONDARY)
VMSTR M/S pin voltage in primary mode 3.9 VIN V
VSLV(0) M/S pin voltage in secondary 0 deg mode 1.25 1.75
VSLV(180) M/S pin voltage in secondary 180 deg mode 0 0.75
ISYNC(in) SYNC pin pull-down current M/S configured as secondary- 0 degrees or
secondary-180 degrees		 8 11 14 µA
VSYNC(in_high) SYNC pin input high-voltage level 2 V
VSYNC(in_low) SYNC pin input low-voltage level 0.8
tSYNC(high_min) Minimum SYNC high pulse-width 40 50 ns
tSYNC(low_min) Minimum SYNC low pulse-width 40 50
GATE DRIVERS
RHDHI High-side driver pull-up resistance CLOAD = 2.2 nF, IDRV = 300 mA 1.37 2.64 3.50 Ω
RHDLO High-side driver pull-down resistance 1.08 2.40 3.35
RLDHI Low-side driver pull-up resistance 1.37 2.40 3.20
RLDLO Low-side driver pull-down resistance 0.44 1.10 1.70
tNON-OVERLAP1 Time delay between HDRV fall and LDRV rise CLOAD = 2.2 nF,
VHDRV = 2 V, VLDRV = 2 V		 50 ns
tNON-OVERLAP2 Time delay between HDRV rise and LDRV fall 60
OVERCURRENT PROTECTION (LOW-SIDE MOSFET SENSING)
IILIM ILIM pin source current 4.5 V < VIN < 60 V, TJ = 25°C 9.00 9.75 10.45 µA
IILIM,(ss) ILIM pin source current during Soft-start 15
IILIM, Tc(1) Temperature coefficient of ILIM current 4.5 V < VIN < 60 V 1400 ppm
VILIM(1) ILIM pin voltage operating range 4.5 V < VIN < 60 V 50 300 mV
OCPTH Overcurrent protection threshold (Voltage across low-side FET for detecting overcurrent) RILIM = 10 kΩ, IILIM = 10 µA
(VILIM = 100 mV)		 –110 –100 –84
SHORT CIRCUIT PROTECTION HIGH-SIDE MOSFET SENSING)
VLDRV(max) LDRV pin maximum voltage during calibration RLDRV = open 300 360 mV
AOC3 Multiplier factor to set the SCP based on OCP level setting at the ILIM pin RLDRV = 10 kΩ 2.75 3.20 3.60 V/V
AOC7 RLDRV = open 6.40 7.25 7.91
AOC15 RLDRV = 20 kΩ 13.9 16.4 18.0
THERMAL SHUTDOWN
TSD,set(1) Thermal shutdown set threshold 4.5 V < VIN < 60 V 155 165 175 °C
TSD,reset(1) Thermal shutdown reset threshold 125 135 145
Thyst(1) Thermal shutdown hysteresis 30
POWERGOOD
VOV FB pin voltage upper limit for power good 4.5 V < VIN < 60 V 627 647 670 mV
VUV FB pin voltage lower limit for power good 527 552 570
VPG,HYST Power good hysteresis voltage at FB pin 8.5 20.0 32.0
VPG(out) PGOOD pin voltage when FB pin voltage > VOV or < VUV, IPGD=2 mA 100
VPG(np) PGOOD pin voltage when device power is removed VIN is open, 10 kΩ to VEXT = 5 V 1 1.5 V
BOOT DIODE
VDFWD Bootstrap diode forward voltage I = 20 mA 0.5 0.7 0.9 V
RBOOT-SW Discharge resistor from BOOT to SW 1 MΩ
(1) Specified by design. Not production tested.