JAJSPO2D June 2010 – October 2024 TLV320AIC3104-Q1
PRODUCTION DATA
A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage. In addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage may have up to seven separate volume controls. These volume controls all have approximately 0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations. Table 8-46 lists the detailed gain versus programmed setting for this basic volume control.
Gain Setting | Analog Gain (dB) |
Gain Setting | Analog Gain (dB) |
Gain Setting | Analog Gain (dB) |
Gain Setting | Analog Gain (dB) |
|||
---|---|---|---|---|---|---|---|---|---|---|
0 | 0 | 30 | –15 | 60 | –30.1 | 90 | –45.2 | |||
1 | –0.5 | 31 | –15.5 | 61 | –30.6 | 91 | –45.8 | |||
2 | –1 | 32 | –16 | 62 | –31.1 | 92 | –46.2 | |||
3 | –1.5 | 33 | –16.5 | 63 | –31.6 | 93 | –46.7 | |||
4 | –2 | 34 | –17 | 64 | –32.1 | 94 | –47.4 | |||
5 | –2.5 | 35 | –17.5 | 65 | –32.6 | 95 | –47.9 | |||
6 | –3 | 36 | –18 | 66 | –33.1 | 96 | –48.2 | |||
7 | –3.5 | 37 | –18.6 | 67 | –33.6 | 97 | –48.7 | |||
8 | –4 | 38 | –19.1 | 68 | –34.1 | 98 | –49.3 | |||
9 | –4.5 | 39 | –19.6 | 69 | –34.6 | 99 | –50 | |||
10 | –5 | 40 | –20.1 | 70 | –35.1 | 100 | –50.3 | |||
11 | –5.5 | 41 | –20.6 | 71 | –35.7 | 101 | –51 | |||
12 | –6 | 42 | –21.1 | 72 | –36.1 | 102 | –51.4 | |||
13 | –6.5 | 43 | –21.6 | 73 | –36.7 | 103 | –51.8 | |||
14 | –7 | 44 | –22.1 | 74 | –37.1 | 104 | –52.2 | |||
15 | –7.5 | 45 | –22.6 | 75 | –37.7 | 105 | –52.7 | |||
16 | –8 | 46 | –23.1 | 76 | –38.2 | 106 | –53.7 | |||
17 | –8.5 | 47 | –23.6 | 77 | –38.7 | 107 | –54.2 | |||
18 | –9 | 48 | –24.1 | 78 | –39.2 | 108 | –55.3 | |||
19 | –9.5 | 49 | –24.6 | 79 | –39.7 | 109 | –56.7 | |||
20 | –10 | 50 | –25.1 | 80 | –40.2 | 110 | –58.3 | |||
21 | –10.5 | 51 | –25.6 | 81 | –40.7 | 111 | –60.2 | |||
22 | –11 | 52 | –26.1 | 82 | –41.2 | 112 | –62.7 | |||
23 | –11.5 | 53 | –26.6 | 83 | –41.7 | 113 | –64.3 | |||
24 | –12 | 54 | –27.1 | 84 | –42.2 | 114 | –66.2 | |||
25 | –12.5 | 55 | –27.6 | 85 | –42.7 | 115 | –68.7 | |||
26 | –13 | 56 | –28.1 | 86 | –43.2 | 116 | –72.2 | |||
27 | –13.5 | 57 | –28.6 | 87 | –43.8 | 117 | –78.3 | |||
28 | –14 | 58 | –29.1 | 88 | –44.3 | 118–127 | Mute | |||
29 | –14.5 | 59 | –29.6 | 89 | –44.8 |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_L Output Routing Control 0: PGA_L is not routed to HPLOUT 1: PGA_L is routed to HPLOUT |
D6–D0 | R/W | 000 0000 | PGA_L to HPLOUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_L1 Output Routing Control 0: DAC_L1 is not routed to HPLOUT. 1: DAC_L1 is routed to HPLOUT. |
D6–D0 | R/W | 000 0000 | DAC_L1 to HPLOUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_R Output Routing Control 0: PGA_R is not routed to HPLOUT 1: PGA_R is routed to HPLOUT |
D6–D0 | R/W | 000 0000 | PGA_R to HPLOUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPLOUT. 1: DAC_R1 is routed to HPLOUT. |
D6–D0 | R/W | 000 0000 | DAC_R1 to HPLOUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | HPLOUT Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved. Do not write these sequences to these register bits. |
D3 | R/W | 0 | HPLOUT Mute 0: HPLOUT is muted. 1: HPLOUT is not muted. |
D2 | R/W | 1 | HPLOUT Power-Down Drive Control 0: HPLOUT is weakly driven to a common-mode when powered down. 1: HPLOUT is high-impedance when powered down. |
D1 | R | 0 | HPLOUT Volume Control Status 0: Not all programmed gains to HPLOUT have been applied yet. 1: All programmed gains to HPLOUT have been applied. |
D0 | R/W | 0 | HPLOUT Power Control 0: HPLOUT is not fully powered up. 1: HPLOUT is fully powered up. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_L Output Routing Control 0: PGA_L is not routed to HPLCOM. 1: PGA_L is routed to HPLCOM. |
D6–D0 | R/W | 000 0000 | PGA_L to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_L1 Output Routing Control 0: DAC_L1 is not routed to HPLCOM. 1: DAC_L1 is routed to HPLCOM. |
D6–D0 | R/W | 000 0000 | DAC_L1 to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_R Output Routing Control 0: PGA_R is not routed to HPLCOM. 1: PGA_R is routed to HPLCOM. |
D6–D0 | R/W | 000 0000 | PGA_R to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPLCOM. 1: DAC_R1 is routed to HPLCOM. |
D6–D0 | R/W | 000 0000 | DAC_R1 to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | HPLCOM Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved. Do not write these sequences to these register bits. |
D3 | R/W | 0 | HPLCOM Mute 0: HPLCOM is muted. 1: HPLCOM is not muted. |
D2 | R/W | 1 | HPLCOM Power-Down Drive Control 0: HPLCOM is weakly driven to a common mode when powered down. 1: HPLCOM is high-impedance when powered down. |
D1 | R | 1 | HPLCOM Volume Control Status 0: Not all programmed gains to HPLCOM have been applied yet. 1: All programmed gains to HPLCOM have been applied. |
D0 | R/W | 0 | HPLCOM Power Control 0: HPLCOM is not fully powered up. 1: HPLCOM is fully powered up. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_L Output Routing Control 0: PGA_L is not routed to HPROUT. 1: PGA_L is routed to HPROUT. |
D6–D0 | R/W | 000 0000 | PGA_L to HPROUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_L1 Output Routing Control 0: DAC_L1 is not routed to HPROUT. 1: DAC_L1 is routed to HPROUT. |
D6–D0 | R/W | 000 0000 | DAC_L1 to HPROUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_R Output Routing Control 0: PGA_R is not routed to HPROUT. 1: PGA_R is routed to HPROUT. |
D6–D0 | R/W | 000 0000 | PGA_R to HPROUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPROUT. 1: DAC_R1 is routed to HPROUT. |
D6–D0 | R/W | 000 0000 | DAC_R1 to HPROUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | HPROUT Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved. Do not write these sequences to these register bits. |
D3 | R/W | 0 | HPROUT Mute 0: HPROUT is muted. 1: HPROUT is not muted. |
D2 | R/W | 1 | HPROUT Power-Down Drive Control 0: HPROUT is weakly driven to a common mode when powered down. 1: HPROUT is high-impedance when powered down. |
D1 | R | 1 | HPROUT Volume Control Status 0: Not all programmed gains to HPROUT have been applied yet. 1: All programmed gains to HPROUT have been applied. |
D0 | R/W | 0 | HPROUT Power Control 0: HPROUT is not fully powered up. 1: HPROUT is fully powered up. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_L Output Routing Control 0: PGA_L is not routed to HPRCOM. 1: PGA_L is routed to HPRCOM. |
D6–D0 | R/W | 000 0000 | PGA_L to HPRCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_L1 Output Routing Control 0: DAC_L1 is not routed to HPRCOM. 1: DAC_L1 is routed to HPRCOM. |
D6–D0 | R/W | 000 0000 | DAC_L1 to HPRCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_R Output Routing Control 0: PGA_R is not routed to HPRCOM. 1: PGA_R is routed to HPRCOM. |
D6–D0 | R/W | 000 0000 | PGA_R to HPRCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPRCOM. 1: DAC_R1 is routed to HPRCOM. |
D6–D0 | R/W | 000 0000 | DAC_R1 to HPRCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | HPRCOM Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved. Do not write these sequences to these register bits. |
D3 | R/W | 0 | HPRCOM Mute 0: HPRCOM is muted. 1: HPRCOM is not muted. |
D2 | R/W | 1 | HPRCOM Power-Down Drive Control 0: HPRCOM is weakly driven to a common mode when powered down. 1: HPRCOM is high-impedance when powered down. |
D1 | R | 1 | HPRCOM Volume Control Status 0: Not all programmed gains to HPRCOM have been applied yet. 1: All programmed gains to HPRCOM have been applied. |
D0 | R/W | 0 | HPRCOM Power Control 0: HPRCOM is not fully powered up. 1: HPRCOM is fully powered up. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved. Do not write to these registers. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0010 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_L Output Routing Control 0: PGA_L is not routed to LEFT_LOP/M. 1: PGA_L is routed to LEFT_LOP/M. |
D6–D0 | R/W | 000 0000 | PGA_L to LEFT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_L1 Output Routing Control 0: DAC_L1 is not routed to LEFT_LOP/M. 1: DAC_L1 is routed to LEFT_LOP/M. |
D6–D0 | R/W | 000 0000 | DAC_L1 to LEFT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_R Output Routing Control 0: PGA_R is not routed to LEFT_LOP/M. 1: PGA_R is routed to LEFT_LOP/M. |
D6–D0 | R/W | 000 0000 | PGA_R to LEFT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_R1 Output Routing Control 0: DAC_R1 is not routed to LEFT_LOP/M. 1: DAC_R1 is routed to LEFT_LOP/M. |
D6–D0 | R/W | 000 0000 | DAC_R1 to LEFT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | LEFT_LOP/M Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved. Do not write these sequences to these register bits. |
D3 | R/W | 0 | LEFT_LOP/M Mute 0: LEFT_LOP/M is muted. 1: LEFT_LOP/M is not muted. |
D2 | R | 0 | Reserved. Do not write to this register bit. |
D1 | R | 1 | LEFT_LOP/M Volume Control Status 0: Not all programmed gains to LEFT_LOP/M have been applied yet. 1: All programmed gains to LEFT_LOP/M have been applied. |
D0 | R/W | 0 | LEFT_LOP/M Power Status 0: LEFT_LOP/M is not fully powered up. 1: LEFT_LOP/M is fully powered up. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_L Output Routing Control 0: PGA_L is not routed to RIGHT_LOP/M. 1: PGA_L is routed to RIGHT_LOP/M. |
D6–D0 | R/W | 000 0000 | PGA_L to RIGHT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_L1 Output Routing Control 0: DAC_L1 is not routed to RIGHT_LOP/M. 1: DAC_L1 is routed to RIGHT_LOP/M. |
D6–D0 | R/W | 000 0000 | DAC_L1 to RIGHT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Reserved. Do not write to this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | PGA_R Output Routing Control 0: PGA_R is not routed to RIGHT_LOP/M. 1: PGA_R is routed to RIGHT_LOP/M. |
D6–D0 | R/W | 000 0000 | PGA_R to RIGHT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | DAC_R1 Output Routing Control 0: DAC_R1 is not routed to RIGHT_LOP/M. 1: DAC_R1 is routed to RIGHT_LOP/M. |
D6–D0 | R/W | 000 0000 | DAC_R1 to RIGHT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 8-46. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | RIGHT_LOP/M Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits. |
D3 | R/W | 0 | RIGHT_LOP/M Mute 0: RIGHT_LOP/M is muted. 1: RIGHT_LOP/M is not muted. |
D2 | R | 0 | Reserved. Do not write to this register bit. |
D1 | R | 1 | RIGHT_LOP/M Volume Control Status 0: All programmed gains to RIGHT_LOP/M have been applied. 1: Not all programmed gains to RIGHT_LOP/M have been applied yet |
D0 | R/W | 0 | RIGHT_LOP/M Power Status 0: RIGHT_LOP/M is not fully powered up. 1: RIGHT_LOP/M is fully powered up. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R | 0 | Left-DAC Power Status 0: Left DAC is not fully powered up. 1: Left DAC is fully powered up. |
D6 | R | 0 | Right-DAC Power Status 0: Right DAC is not fully powered up. 1: Right DAC is fully powered up. |
D5 | R | 0 | Reserved. Write only 0 to this bit. |
D4 | R | 0 | LEFT_LOP/M Power Status 0: LEFT_LOP/M output driver is powered down. 1: LEFT_LOP/M output driver is powered up. |
D3 | R | 0 | RIGHT_LOP/M Power Status 0: RIGHT_LOP/M is not fully powered up. 1: RIGHT_LOP/M is fully powered up. |
D2 | R | 0 | HPLOUT Driver Power Status 0: HPLOUT Driver is not fully powered up. 1: HPLOUT Driver is fully powered up. |
D1 | R | 0 | HPROUT Driver Power Status 0: HPROUT Driver is not fully powered up. 1: HPROUT Driver is fully powered up. |
D0 | R | 0 | Reserved. Do not write to this bit. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R | 0 | HPLOUT Short-Circuit Detection Status 0: No short circuit detected at HPLOUT 1: Short circuit detected at HPLOUT |
D6 | R | 0 | HPROUT Short-Circuit Detection Status 0: No short circuit detected at HPROUT 1: Short circuit detected at HPROUT |
D5 | R | 0 | HPLCOM Short-Circuit Detection Status 0: No short circuit detected at HPLCOM 1: Short circuit detected at HPLCOM |
D4 | R | 0 | HPRCOM Short-Circuit Detection Status 0: No short circuit detected at HPRCOM 1: Short circuit detected at HPRCOM |
D3 | R | 0 | HPLCOM Power Status 0: HPLCOM is not fully powered up. 1: HPLCOM is fully powered up. |
D2 | R | 0 | HPRCOM Power Status 0: HPRCOM is not fully powered up. 1: HPRCOM is fully powered up. |
D1–D0 | R | 00 | Reserved. Do not write to these bits. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R | 0 | HPLOUT Short-Circuit Detection Status 0: No short circuit detected at HPLOUT driver 1: Short circuit detected at HPLOUT driver |
D6 | R | 0 | HPROUT Short-Circuit Detection Status 0: No short circuit detected at HPROUT driver 1: Short circuit detected at HPROUT driver |
D5 | R | 0 | HPLCOM Short-Circuit Detection Status 0: No short circuit detected at HPLCOM driver 1: Short circuit detected at HPLCOM driver |
D4 | R | 0 | HPRCOM Short-Circuit Detection Status 0: No short circuit detected at HPRCOM driver 1: Short circuit detected at HPRCOM driver |
D3 | R | 0 | Reserved. Do not write to this bit. |
D2 | R | 0 | Headset Detection Status 0: No headset insertion/removal is detected. 1: Headset insertion/removal is detected. |
D1 | R | 0 | Left ADC AGC Noise Gate Status 0: Left ADC signal power is greater than or equal to noise threshold for left AGC. 1: Left ADC signal power is less than noise threshold for left AGC. |
D0 | R/W | 0 | Right ADC AGC Noise Gate Status 0: Right ADC signal power is greater than or equal to noise threshold for right AGC. 1: Right ADC signal power is less than noise threshold for right AGC. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R | 0 | HPLOUT Short-Circuit Detection Status 0: No short circuit detected at HPLOUT driver 1: Short circuit detected at HPLOUT driver |
D6 | R | 0 | HPROUT Short-Circuit Detection Status 0: No short circuit detected at HPROUT driver 1: Short circuit detected at HPROUT driver |
D5 | R | 0 | HPLCOM Short-Circuit Detection Status 0: No short circuit detected at HPLCOM driver 1: Short circuit detected at HPLCOM driver |
D4 | R | 0 | HPRCOM Short-Circuit Detection Status 0: No short circuit detected at HPRCOM driver 1: Short circuit detected at HPRCOM driver |
D3 | R | 0 | Reserved. Do not write to this bit. |
D2 | R | 0 | Headset Detection Status 0: No headset insertion/removal is detected. 1: Headset insertion/removal is detected. |
D1 | R | 0 | Left ADC AGC Noise Gate Status 0: Left ADC signal power is greater than noise threshold for left AGC. 1: Left ADC signal power lower than noise threshold for left AGC. |
D0 | R | 0 | Right ADC AGC Noise Gate Status 0: Right ADC signal power is greater than noise threshold for right AGC. 1: Right ADC signal power is lower than noise threshold for right AGC. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved. Do not write to these registers. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D1 | R | 0000 000 | Reserved. Write only zeros to these bits.((1)) |
D0 | R/W | 0 | CODEC_CLKIN Source Selection 0: CODEC_CLKIN uses PLLDIV_OUT 1: CODEC_CLKIN uses CLKDIV_OUT |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | CLKDIV_IN Source Selection 00: CLKDIV_IN uses MCLK. 01: CLKDIV_IN uses GPIO2. 10: CLKDIV_IN uses BCLK. 11: Reserved. Do not use. |
D5–D4 | R/W | 00 | PLLCLK_IN Source Selection 00: PLLCLK_IN uses MCLK. 01: PLLCLK_IN uses GPIO2. 10: PLLCLK _IN uses BCLK. 11: Reserved. Do not use. |
D3–D0 | R/W | 0010 | Reserved. Write only 0010 to these bits. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Attack Time Register Selection 0: Attack time for the left AGC is generated from page 0, register 26. 1: Attack time for the left AGC is generated from this register. |
D6–D5 | R/W | 00 | Baseline AGC Attack time 00: Left-AGC attack time = 7 ms 01: Left-AGC attack time = 8 ms 10: Left-AGC attack time = 10 ms 11: Left-AGC attack time = 11 ms |
D4–D2 | R/W | 000 | Multiplication Factor for Baseline AGC 000: Multiplication factor for the baseline AGC attack time = 1 001: Multiplication factor for the baseline AGC attack time = 2 010: Multiplication factor for the baseline AGC attack time = 4 011: Multiplication factor for the baseline AGC attack time = 8 100: Multiplication factor for the baseline AGC attack time = 16 101: Multiplication factor for the baseline AGC attack time = 32 110: Multiplication factor for the baseline AGC attack time = 64 111: Multiplication factor for the baseline AGC attack time = 128 |
D1–D0 | R/W | 00 | Reserved. Write only zeros to these bits. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Decay Time Register Selection (1) 0: Decay time for the left AGC is generated from page 0, register 26. 1: Decay time for the left AGC is generated from this register. |
D6–D5 | R/W | 00 | Baseline AGC Decay Time 00: Left-AGC decay time = 50 ms 01: Left-AGC decay time = 150 ms 10: Left-AGC decay time = 250 ms 11: Left-AGC decay time = 350 ms |
D4–D2 | R/W | 000 | Multiplication Factor for Baseline AGC 000: Multiplication factor for the baseline AGC decay time = 1 001: Multiplication factor for the baseline AGC decay time = 2 010: Multiplication factor for the baseline AGC decay time = 4 011: Multiplication factor for the baseline AGC decay time = 8 100: Multiplication factor for the baseline AGC decay time = 16 101: Multiplication factor for the baseline AGC decay time = 32 110: Multiplication factor for the baseline AGC decay time = 64 111: Multiplication factor for the baseline AGC decay time = 128 |
D1–D0 | R/W | 00 | Reserved. Write only zeros to these bits. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Attack Time Register Selection 0: Attack time for the right AGC is generated from page 0, register 29. 1: Attack time for the right AGC is generated from this register. |
D6–D5 | R/W | 00 | Baseline AGC attack time 00: Right-AGC attack time = 7 ms 01: Right-AGC attack time = 8 ms 10: Right-AGC attack time = 10 ms 11: Right-AGC attack time = 11 ms |
D4–D2 | R/W | 000 | Multiplication Factor for Baseline AGC 000: Multiplication factor for the baseline AGC attack time = 1 001: Multiplication factor for the baseline AGC attack time = 2 010: Multiplication factor for the baseline AGC attack time = 4 011: Multiplication factor for the baseline AGC attack time = 8 100: Multiplication factor for the baseline AGC attack time = 16 101: Multiplication factor for the baseline AGC attack time = 32 110: Multiplication factor for the baseline AGC attack time = 64 111: Multiplication factor for the baseline AGC attack time = 128 |
D1–D0 | R/W | 00 | Reserved. Write only zeros to these bits. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Decay Time Register Selection(1)
0: Decay time for the right AGC is generated from page 0, register 29. 1: Decay time for the right AGC is generated from this register. |
D6–D5 | R/W | 00 | Baseline AGC Decay Time 00: Right-AGC decay time = 50 ms 01: Right-AGC decay time = 150 ms 10: Right-AGC decay time = 250 ms 11: Right-AGC decay time = 350 ms |
D4–D2 | R/W | 000 | Multiplication Factor for Baseline AGC 000: Multiplication factor for the baseline AGC decay time = 1 001: Multiplication factor for the baseline AGC decay time = 2 010: Multiplication factor for the baseline AGC decay time = 4 011: Multiplication factor for the baseline AGC decay time = 8 100: Multiplication factor for the baseline AGC decay time = 16 101: Multiplication factor for the baseline AGC decay time = 32 110: Multiplication factor for the baseline AGC decay time = 64 111: Multiplication factor for the baseline AGC decay time = 128 |
D1–D0 | R/W | 00 | Reserved. Write only zeros to these bits. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Left-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled. 1: Programmable coefficients are used when ADC high pass is enabled. |
D6 | R/W | 0 | Right-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled. 1: Programmable coefficients are used when ADC high pass is enabled. |
D5–D4 | R/W | 00 | ADC Decimation Filter Configuration 00: Left and right digital microphones are used. 01: Left digital microphone and right analog microphone are used. 10: Left analog microphone and right digital microphone are used. 11: Left and right analog microphones are used. |
D3 | R/W | 0 | ADC Digital Output to Programmable Filter Path
Selection 0: No additional programmable filters other than the HPF are used for the ADC. 1: The programmable filter is connected to ADC output, if both DACs are powered down. |
D2 | R/W | 0 | I2C Bus Condition Detector 0: Internal logic is enabled to detect an I2C bus error, and clears the bus error condition. 1: Internal logic is disabled to detect an I2C bus error. |
D1 | R | 0 | Reserved. Write only zero to these register bits. |
D0 | R | 0 | I2C Bus Error Detection Status 0: I2C bus error is not detected. 1: I2C bus error is detected. This bit is cleared by reading this register. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Reserved. Write only zero to this bit. |
D6 | R/W | 0 | Reserved. Write only zero to these register bits. |
D5 | R/W | 0 | LINE1RM Path Selection 0: Normal signal path 1: Signal is routed by a switch to RIGHT_LOM. |
D4 | R/W | 0 | LINE1RP Path Selection 0: Normal signal path 1: Signal is routed by a switch to RIGHT_LOP. |
D3 | R/W | 0 | Reserved. Write only zero to this bit. |
D2 | R/W | 0 | Reserved. Write only zero to these register bits. |
D1 | R/W | 0 | LINE1LM Path Selection 0: Normal signal path 1: Signal is routed by a switch to LEFT_LOM. |
D0 | R/W | 0 | LINE1LP Path Selection 0: Normal signal path 1: Signal is routed by a switch to LEFT_LOP. |
Based on the register 108 settings, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches used for the connection short the two input signals together on the output pins. The shorting resistance between the two input pins is two times the bypass switch resistance (RDS(ON)). In general, this condition of shorting should be avoided, as higher drive currents are likely to occur on the circuitry that feeds these two input pins of this device.
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | DAC Current Adjustment 00: Default 01: 50% increase in DAC reference current 10: Reserved 11: 100% increase in DAC reference current |
D5–D0 | R/W | 00 0000 | Reserved. Write only zeros to these bits. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved. Do not write to these registers. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D1 | X | 0000 000 | Reserved, write only zeros to these bits. |
D0 | R/W | 0 | Page Select Bit Writing zero to this bit sets page 0 as the active page for following register accesses. Writing a one to this bit sets page 1 as the active page for following register accesses. It is recommended that the user read this register bit back after each write, to ensure that the proper page is being accessed for future register read/writes. This register has the same functionality on page 0 and page 1. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 1011 | Left-Channel Audio Effects Filter N0 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 0011 | Left-Channel Audio Effects Filter N0 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1001 0110 | Left-Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0110 | Left-Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0111 | Left-Channel Audio Effects Filter N2 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 1101 | Left-Channel Audio Effects Filter N2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 1011 | Left-Channel Audio Effects Filter N3 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 0011 | Left-Channel Audio Effects Filter N3 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1001 0110 | Left-Channel Audio Effects Filter N4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0110 | Left-Channel Audio Effects Filter N4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0111 | Left-Channel Audio Effects Filter N5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 1101 | Left-Channel Audio Effects Filter N5 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1101 | Left-Channel Audio Effects Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0011 | Left-Channel Audio Effects Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0100 | Left-Channel Audio Effects Filter D2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 1110 | Left-Channel Audio Effects Filter D2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1101 | Left-Channel Audio Effects Filter D4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0011 | Left-Channel Audio Effects Filter D4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0100 | Left-Channel Audio Effects Filter D5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 1110 | Left-Channel Audio Effects Filter D5 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0011 1001 | Left-Channel De-Emphasis Filter N0 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0101 | Left-Channel De-Emphasis Filter N0 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1111 0011 | Left-Channel De-Emphasis Filter N1 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0010 1101 | Left-Channel De-Emphasis Filter N1 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0011 | Left-Channel De-Emphasis Filter D1 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1110 | Left-Channel De-Emphasis Filter D1 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 1011 | Right-Channel Audio Effects Filter N0 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 0011 | Right-Channel Audio Effects Filter N0 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1001 0110 | Right-Channel Audio Effects Filter N1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0110 | Right-Channel Audio Effects Filter N1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0111 | Right-Channel Audio Effects Filter N2 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 1101 | Right-Channel Audio Effects Filter N2 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 1011 | Right-Channel Audio Effects Filter N3 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 0011 | Right-Channel Audio Effects Filter N3 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1001 0110 | Right-Channel Audio Effects Filter N4 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0110 | Right-Channel Audio Effects Filter N4 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0110 0111 | Right-Channel Audio Effects Filter N5 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 1101 | Right-Channel Audio Effects Filter N5 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1101 | Right-Channel Audio Effects Filter D1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0011 | Right-Channel Audio Effects Filter D1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0100 | Right-Channel Audio Effects Filter D2 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 1110 | Right-Channel Audio Effects Filter D2 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1101 | Right-Channel Audio Effects Filter D4 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0011 | Right-Channel Audio Effects Filter D4 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1000 0100 | Right-Channel Audio Effects Filter D5 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 1110 | Right-Channel Audio Effects Filter D5 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0011 1001 | Right-Channel De-Emphasis Filter N0 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0101 | Right-Channel De-Emphasis Filter N0 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1111 0011 | Right-Channel De-Emphasis Filter N1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0010 1101 | Right-Channel De-Emphasis Filter N1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0011 | Right-Channel De-Emphasis Filter D1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1110 | Right-Channel De-Emphasis Filter D1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1111 | 3-D Attenuation Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1111 1111 | 3-D Attenuation Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved. Do not write to these registers. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0011 1001 | Left-Channel ADC High-Pass Filter N0 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0101 | Left-Channel ADC High-Pass Filter N0 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1111 0011 | Left-Channel ADC High-Pass Filter N1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0010 1101 | Left-Channel ADC High-Pass Filter N1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0011 | Left-Channel ADC High-Pass Filter D1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1110 | Left-Channel ADC High-Pass Filter D1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0011 1001 | Right-Channel ADC High-Pass Filter N0 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0101 | Right-Channel ADC High-Pass Filter N0 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1111 0011 | Right-Channel ADC High-Pass Filter N1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0010 1101 | Right-Channel ADC High-Pass Filter N1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0101 0011 | Right-Channel ADC High-Pass Filter D1 Coefficient
MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1110 | Right-Channel ADC High-Pass Filter D1 Coefficient
LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. |
BIT | READ/ WRITE |
RESET VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved. Do not write to these registers. |