JAJSPO2D June   2010  – October 2024 TLV320AIC3104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 6.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  Switching Characteristics DSP Timing in Master Mode
    9. 6.9  Switching Characteristics DSP Timing in Slave Mode
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Audio Data Converters
      2. 7.3.2  Stereo Audio ADC
        1. 7.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 7.3.3  Automatic Gain Control (AGC)
      4. 7.3.4  Stereo Audio DAC
      5. 7.3.5  Digital Audio Processing for Playback
      6. 7.3.6  Digital Interpolation Filter
      7. 7.3.7  Delta-Sigma Audio DAC
      8. 7.3.8  Audio DAC Digital Volume Control
      9. 7.3.9  Analog Output Common-mode Adjustment
      10. 7.3.10 Audio DAC Power Control
      11. 7.3.11 Audio Analog Inputs
      12. 7.3.12 Analog Input Bypass Path Functionality
      13. 7.3.13 ADC PGA Signal Bypass Path Functionality
      14. 7.3.14 Input Impedance and VCM Control
      15. 7.3.15 MICBIAS Generation
      16. 7.3.16 Analog Fully Differential Line Output Drivers
      17. 7.3.17 Analog High-Power Output Drivers
      18. 7.3.18 Short-Circuit Output Protection
      19. 7.3.19 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Audio Processing for Record Path
      2. 7.4.2 Increasing DAC Dynamic Range
      3. 7.4.3 Passive Analog Bypass During Power Down
      4. 7.4.4 Hardware Reset
    5. 7.5 Programming
      1. 7.5.1  Digital Control Serial Interface
      2. 7.5.2  I2C Control Interface
      3. 7.5.3  I2C Bus Debug in a Glitched System
      4. 7.5.4  Digital Audio Data Serial Interface
      5. 7.5.5  Right-Justified Mode
      6. 7.5.6  Left-Justified Mode
      7. 7.5.7  I2S Mode
      8. 7.5.8  DSP Mode
      9. 7.5.9  TDM Data Transfer
      10. 7.5.10 Audio Clock Generation
  9. 8 Register Maps
    1. 8.1 Output Stage Volume Controls
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.1 Audio Data Converters

The TLV320AIC3104-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at different sampling rates in various combinations, which are described further as follows.

The data converters are based on the concept of an fS(ref) rate that is used internal to the device, and is related to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, fS(ref) is either 44.1 kHz or 48 kHz, although fS(ref) can realistically be set over a wider range of rates up to 53 kHz, with additional restrictions if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and also to enable high-quality playback of low-sampling-rate data without high-frequency audible noise being generated.

The sampling rate of the ADC and DAC is determined by the clock divider (NCODEC). The sampling rate can be set to fS(ref) / NCODEC or 2 × fS(ref) / NCODEC, with NCODEC being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3104-Q1, NDAC and NADC must be set to the same value because the device only supports a common sampling rate for the ADC and DAC channels. Therefore, NCODEC = NDAC = NADC and this value is programmed by setting the value of bits D7 to D4 equal to the value of bits D3 to D0 in register 2, page 0.