The power-good feature using the PG pin of the LMR36503E-Q1 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under device fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and load transients. Output voltage excursions lasting less than t_{RESET_FILTER} do not trip the power-good flag. Power-good operation can best be understood in reference to Figure 7-8. Table 7-3 gives a more detailed breakdown the PGOOD operation. Here, V_PG-UV is defined as the PG-UV scaled version of the V_OUT-Reg (target regulated output voltage) and V_PG-HYS as the PG-HYS scaled version of the V_OUT-Reg, where both PG-UV and PG-HYS are listed in Section 6.5. During the initial power up, a total delay of 5ms (typical) is encountered from the time the V_EN-VOUT is triggered to the time that the power-good is flagged high. This delay only occurs during the device start-up and is not encountered during any other normal operation of the power-good function. When EN is pulled low, the power-good flag output is also forced low. With EN low, power-good remains valid as long as the input voltage (V_PG-VALID is ≥ 1V (typical).

The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup resistor connected to a suitable logic supply. The power-good output scheme can also be pulled up to either V_CC or V_OUT through an appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit the current into this pin to ≤ 4mA.

Figure 7-8 Power-Good Operation (OV Events Not Included)