JAJSPW8E march   2011  – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions – LVDS Mode
    2.     Pin Functions – CMOS Mode
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 7.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes #GUID-C6C0701B-A11B-492F-BD6B-B774F5FE4665/SLAS6895399
    10. 7.10 Serial Interface Timing Characteristics #GUID-3852E7CE-C5B6-42F5-A56A-70AB1B981302/SBAS5097810
    11. 7.11 Reset Timing (Only When Serial Interface Is Used)
    12. 7.12 Typical Characteristics
      1. 7.12.1 ADS4246
      2. 7.12.2 ADS4245
      3. 7.12.3 ADS4242
      4. 7.12.4 ADS4226
      5. 7.12.5 ADS4225
      6. 7.12.6 ADS4222
      7. 7.12.7 General
      8. 7.12.8 Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Drive Circuit Requirements
        2. 8.3.1.2 Driving Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 Digital Functions
      4. 8.3.4 Gain for SFDR/SNR Trade-off
      5. 8.3.5 Offset Correction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down
        1. 8.4.1.1 Global Power-Down
        2. 8.4.1.2 Channel Standby
        3. 8.4.1.3 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 47
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
      7. 8.5.7 Digital Output Information
        1. 8.5.7.1 Output Interface
        2. 8.5.7.2 DDR LVDS Outputs
        3. 8.5.7.3 LVDS Buffer
        4. 8.5.7.4 Parallel CMOS Interface
        5. 8.5.7.5 CMOS Interface Power Dissipation
        6. 8.5.7.6 Multiplexed Mode of Operation
        7. 8.5.7.7 Output Data Format
    6. 8.6 Register Maps
      1. 8.6.1 64
      2. 8.6.2 Description Of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
        4. 9.2.2.4 SNR and Clock Jitter
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Sharing DRVDD and AVDD Supplies
      2. 9.3.2 Using DC/DC Power Supplies
      3. 9.3.3 Power Supply Bypassing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Grounding
        2. 9.4.1.2 Supply Decoupling
        3. 9.4.1.3 Exposed Pad
        4. 9.4.1.4 Routing Analog Inputs
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

7.11 Reset Timing (Only When Serial Interface Is Used)

See the Serial Register Readout section.
PARAMETER CONDITIONS MIN TYP(1) MAX UNIT
t1 Power-on delay Delay from AVDD and DRVDD power-up to active RESET pulse 1 ms
t2 Reset pulse width Active RESET signal pulse width 10 ns
1 µs
t3 Register write delay Delay from RESET disable to SEN active 100 ns
(1) Typical values at 25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C, unless otherwise noted.
Table 7-1 LVDS Timings at Lower Sampling Frequencies
SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) HOLD TIME (ns) tPDI, CLOCK PROPAGATION
DELAY (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 5.9 6.6 0.35 0.6 5 6.1 7.5
80 4.5 5.2 0.35 0.6 5 6.1 7.5
105 3.1 3.6 0.35 0.6 5 6.1 7.5
125 2.3 2.9 0.35 0.6 5 6.1 7.5
150 1.7 2.2 0.35 0.6 5 6.1 7.5
Table 7-2 CMOS Timings at Lower Sampling Frequencies
SAMPLING FREQUENCY (MSPS) TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SETUP TIME (ns) HOLD TIME (ns) tPDI, CLOCK PROPAGATION
DELAY (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 6.1 7.2 6.7 7.1 4.5 6.4 8.5
80 4.7 5.8 5.3 5.8 4.5 6.4 8.5
105 3.4 4.3 3.8 4.3 4.5 6.4 8.5
125 2.7 3.6 3.1 3.6 4.5 6.4 8.5
150 1.9 2.8 2.5 2.9 4.5 6.4 8.5
Table 7-3 High-Performance Modes
PARAMETER(1)(2) DESCRIPTION
High-performance mode Set the HIGH PERF MODE register bit to obtain best performance across sample clock and input signal frequencies. See Figure 7-5.
Register address = 03h, data = 03h
High-frequency mode Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input signal frequencies greater than 200 MHz. See Figure 7-5.
Register address = 4Ah, data = 01h
Register address = 58h, data = 01h
(1) It is recommended to use these modes to obtain best performance.
(2) See the Serial Interface Configuration section for details on register programming.
GUID-56F92B03-4387-4AB7-8F80-76B49E5F44FC-low.gif
A. Dn = bits D0, D1, D2, etc. of channels A and B.
Figure 7-1 CMOS Interface Timing Diagram
GUID-A6E39278-697C-4BFD-A37A-872525573BB3-low.gif
A. ADC latency after reset. At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency = ADC latency + 1.
B. E = even bits (D0, D2, D4, etc.); O = odd bits (D1, D3, D5, etc.).
Figure 7-2 Latency Timing Diagram
GUID-EA94FFE6-D486-4431-83D8-56F49A557B4F-low.gif Figure 7-3 ADS4246/45/42 LVDS Interface Timing Diagram
GUID-180F4024-F737-4AA3-BA53-F6735E2B0515-low.gif Figure 7-4 ADS4226/25/22 LVDS Interface Timing Diagram
GUID-4DA3BD04-6F13-4DC7-A628-F7F49965D766-low.gif
A. With external 100-Ω termination.
Figure 7-5 LVDS Output Voltage Levels