JAJSQ80C september 2013 – october 2020 SN65DSI86
PRODUCTION DATA
The clock source for the SN65DSI86 is derived from one of two sources: REFCLK pin or DACP/N pins. On the rising edge of EN, the sampled state of GPIO[3:1] as well as the detection of a clock on REFCLK pin is used to determine the clock source and the frequency of that clock. After the EN, software through the I2C interface can change the configuration of REFCLK_FREQ, and CHA_DSI_CLK_RANGE registers for the case where GPIO[3:1] sampled state does not represent the intended functionality. Because the clock source is determined at the assertion of EN, software can not change the clock source. See Table 8-1 for GPIO to REFCLK or DACP/N frequency combinations.
| GPIO[3:1] | REFCLK FREQUENCY (DPPLL_CLK_SRC = 0) | DACP/N CLOCK FREQUENCY (DPPLL_CLK_SRC = 1) | REFCLK_FREQ |
|---|---|---|---|
| 3’b000 | 12 MHz | 468 MHz (DSIACLK / 39 = 12 MHz ) | 0x0 |
| 3’b001 | 19.2 MHz | 384 MHz (DSIACLK / 20 = 19.2 MHz) | 0x1 |
| 3’b010 | 26 MHz | 416 MHz (DSIACLK / 16 = 26 MHz) | 0x2 |
| 3’b011 | 27 MHz | 486 MHz (DSIACLK / 18 = 27 MHz) | 0x3 |
| 3’b100 | 38.4 MHz | 460.8 MHz (DSIACLK / 12 = 38.4 MHz) | 0x4 |
| 3’b101 through 3’b111 | 19.2 MHz | 384 MHz (DSIACLK / 20 = 19.2 MHz) | 0x5 through 0x7 |