JAJSQ81F December   2015  – December 2023 TUSB542

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply Currents
    6. 5.6  Electrical Characteristics, DC
    7. 5.7  Electrical Characteristics, Dynamic
    8. 5.8  Electrical Characteristics, AC
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
      1. 5.11.1 1-Inch Pre Channel
      2. 5.11.2 24-Inch Pre Channel
      3. 5.11.3 32-Inch Pre Channel
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Receiver Equalization
      2. 6.3.2 De-Emphasis Control and Output Swing
      3. 6.3.3 Automatic LFPS Detection
      4. 6.3.4 Automatic Power Management
    4. 6.4 Device Functional Modes
      1. 6.4.1 Disconnect Mode
      2. 6.4.2 U Modes
        1. 6.4.2.1 U0 Mode
        2. 6.4.2.2 U2/U3 Mode
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications, USB Type-C Port SS MUX
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Typical Application: Switching USB SS Host or Device Ports
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curves
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Layout Guidelines

  • RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
  • Keep away from other high speed signals.
  • Intra-pair routing should be kept to within 2 mils.
  • Length matching should be near the location of mismatch.
  • Each pair should be separated at least by 3 times the signal trace width.
  • The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
  • Route all differential pairs on the same of layer.
  • The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
  • Keep traces on layers adjacent to ground plane.
  • Do not route differential pairs over any plane split.
  • Adding test points will cause impedance discontinuity, and therefore; negatively impacts signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.