JAJSQU6A January   2024  – June 2024 TPS56837H

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  The Adaptive On-Time Control and PWM Operation
      2. 6.3.2  Mode Selection
      3. 6.3.3  Eco-mode Control Scheme
      4. 6.3.4  Soft Start and Prebiased Soft Start
      5. 6.3.5  Enable and Adjusting Undervoltage Lockout
      6. 6.3.6  Output Overcurrent Limit and Undervoltage Protection
      7. 6.3.7  Overvoltage Protection
      8. 6.3.8  UVLO Protection
      9. 6.3.9  Thermal Shutdown
      10. 6.3.10 Output Voltage Discharge
      11. 6.3.11 Power Good
      12. 6.3.12 Large Duty Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Operation
      2. 6.4.2 Light Load Operation
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Resistors Selection
        2. 7.2.2.2 Output Filter Selection
        3. 7.2.2.3 Input Capacitor Selection
        4. 7.2.2.4 Bootstrap Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

The Adaptive On-Time Control and PWM Operation

The main control loop of the TPS56837H and TPS56837HA is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP3 control mode. The D-CAP3 control mode combines adaptive on-time control with an internal compensation circuit for quasi-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. The D-CAP3 control mode is stable even with virtually no ripple at the output. The TPS56837H and TPS56837HA also include error amplifier that makes the output voltage very accurate. No external current sense network or loop compensation is required for D-CAP3 control mode topology.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one-shot timer expires. This one-shot duration is set proportional to the output voltage VOUT, and is inversely proportional to the converter input voltage VIN, to maintain a pseudo-fixed frequency over the input voltage range, hence called adaptive on-time control. When the feedback voltage falls below the reference voltage, the one-shot timer is reset and the high-side MOSFET is turned on again. An internal ripple generation circuit is added to reference voltage for emulating the output ripple, and this enables the use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC).