JAJSQU6A January   2024  – June 2024 TPS56837H

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  The Adaptive On-Time Control and PWM Operation
      2. 6.3.2  Mode Selection
      3. 6.3.3  Eco-mode Control Scheme
      4. 6.3.4  Soft Start and Prebiased Soft Start
      5. 6.3.5  Enable and Adjusting Undervoltage Lockout
      6. 6.3.6  Output Overcurrent Limit and Undervoltage Protection
      7. 6.3.7  Overvoltage Protection
      8. 6.3.8  UVLO Protection
      9. 6.3.9  Thermal Shutdown
      10. 6.3.10 Output Voltage Discharge
      11. 6.3.11 Power Good
      12. 6.3.12 Large Duty Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Operation
      2. 6.4.2 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Resistors Selection
        2. 7.2.2.2 Output Filter Selection
        3. 7.2.2.3 Input Capacitor Selection
        4. 7.2.2.4 Bootstrap Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.2 Output Filter Selection

The LC filter used as the output filter has double pole at:

Equation 7. fp=12π×LOUT×COUT

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. D-CAP3 control mode introduces a high frequency zero that reduces the gain roll off to –20dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 7 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 7-2.

Table 7-2 Recommended Component Values

Switching Frequency (kHz)

Output Voltage(1) (V)R6 (kΩ)R7 (kΩ)L1 (µH)COUT(2) (µF)C10 (3)(pF)

Typical

Maximum

500

5304.1

4.7

22uF × 4

22uF × 10

150

9302.15

4.7

22uF × 4

22uF × 10

150

15301.24

4.7

22uF × 4

22uF × 10

150

20300.93

4.7

22uF × 4

22uF × 10

150

(1) Please use the recommended L1 and COUT combination of the higher and closest output rail for unlisted output rails.
(2) COUT in this data sheet is using TDK C3216X5R1V226M160AC 35VDC capacitor. TI recommends to use the same effective output capacitance. The effective capacitance is defined as the actual capacitance under DC bias and temperature, not the rated or nameplate values. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. A careful study of bias and temperature variation of any capacitor bank must be made to make sure that the minimum value of effective capacitance is provided. Refer to the information of DC bias and temperature characteristics from manufacturers of ceramic capacitors. Higher than Cout_max capacitance is allowed by careful tuning the feedforward compensation.
(3) C10 can be used to improve the load transient response or improve the loop-phase margin. The Optimizing Transient Response of Internally Compensated DCDC Converters with Feed-forward Capacitor application report is helpful when experimenting with a feed-forward capacitor.

Calculate the inductor peak-to-peak ripple current, peak current and RMS current using Equation 8, Equation 9, and Equation 10. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Use 500kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 9 and the RMS current of Equation 10.

Equation 8. Ilp-p=VOUTVINMAX×VINMAX-VOUTLOUT×Fsw
Equation 9. IlPEAK=IO+Ilp-p2
Equation 10. ILORMS=IO2+112×Ilp-p2

The capacitor value and ESR determines the amount of output voltage ripple. The TPS56837H is intended for use with ceramic or other low ESR capacitors. Use Equation 11 to determine the required RMS current rating for the output capacitor.

Equation 11. ICORMS=VOUT×VIN-VOUT12×VIN×LOUT×Fsw