JAJSR60F August   2008  – June 2020 TPS40210-Q1 , TPS40211-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5.   5
  6. 4 Revision History
  7. 5 Pin Configuration and Functions
    1.     Pin Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum On-Time and Off-Time Considerations
      2. 7.3.2  Current Sense and Overcurrent
      3. 7.3.3  Current Sense and Subharmonic Instability
      4. 7.3.4  Current Sense Filtering
      5. 7.3.5  Soft Start
      6. 7.3.6  BP Regulator
      7. 7.3.7  Shutdown (DIS/ EN Pin)
      8. 7.3.8  Control Loop Considerations
      9. 7.3.9  Gate Drive Circuit
      10. 7.3.10 TPS40211-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Setting the Oscillator Frequency
      2. 7.4.2 Synchronizing the Oscillator
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Duty Cycle Estimation
        2. 8.2.2.2  Inductor Selection
        3. 8.2.2.3  Rectifier Diode Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Current Sense and Current Limit
        7. 8.2.2.7  Current Sense Filter
        8. 8.2.2.8  Switching MOSFET Selection
        9. 8.2.2.9  Feedback Divider Resistors
        10. 8.2.2.10 Error Amplifier Compensation
        11. 8.2.2.11 R-C Oscillator
        12. 8.2.2.12 Soft-Start Capacitor
        13. 8.2.2.13 Regulator Bypass
      3. 8.2.3 Application Curves
  11. 9 Power Supply Recommendations
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  14. 12Mechanical, Packaging, and Orderable Information
    1.     70

8.2.2.8 Switching MOSFET Selection

The TPS40210-Q1 device drives a ground referenced N-channel FET. The RDS(on) and gate charge are estimated based on the desired efficiency target.

Equation 52. GUID-FE4FA5B7-3D4C-41EB-8C67-93EB042CCEFA-low.gif

For a target of 95% efficiency with a 24-V input voltage at 2 A, maximum power dissipation is limited to 2.526 W. The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated circuit, the TPS40210-Q1 device.

Equation 53. GUID-2AA20596-4FA9-4B1D-9924-44C8A5573439-low.gif

This leaves 740 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, you can determine a target RDS(on) and QGS for the MOSFET by Equation 54 and Equation 55.

Equation 54. GUID-5D13D404-4F3E-4F24-9991-838AE6F8A1F8-low.gif

A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less than 250 mW.

Equation 55. GUID-10E022F1-094A-41EF-ACF5-623B0B5115F3-low.gif

A target MOSFET RDS(on) of 9.8 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing 30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per Equation 29. The maximum gate charge at Vgs = 8 V for the Si4386DY is 33.2 nC, this implies RG = 3.3 Ω.