JAJSR60F August 2008 – June 2020 TPS40210-Q1 , TPS40211-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VOLTAGE REFERENCE | ||||||||
VFB | Feedback voltage range | TPS40210-Q1 | COMP = FB, 4.5 ≤ VDD ≤ 52 V | TJ = 25°C | 693 | 700 | 707 | mV |
–40°C ≤ TJ ≤ 125°C | 686 | 700 | 714 | |||||
TPS40211-Q1 | COMP = FB, 4.5 ≤ VDD ≤ 52 V | TJ = 25°C | 254 | 260 | 266 | |||
–40°C ≤ TJ ≤ 125°C | 250 | 260 | 270 | |||||
INPUT SUPPLY | ||||||||
IDD | Operating current | 4.5 ≤ VDD ≤ 52 V, no switching, VDIS < 0.8 | 1.5 | 2.5 | mA | |||
2.5 ≤ VDIS ≤ 7 V | 10 | 20 | μA | |||||
VDD < VUVLO(on), VDIS < 0.8 | 530 | |||||||
UNDERVOLTAGE LOCKOUT (UVLO) | ||||||||
VUVLO(on) | Turnon threshold voltage | 4 | 4.25 | 4.5 | V | |||
VUVLO(hyst) | UVLO hysteresis | 140 | 195 | 240 | mV | |||
Frequency line regulation | 4.5 ≤ VDD ≤ 52 V | –20% | 7% | |||||
7 ≤ VDD ≤ 52 V | –10% | 7% | ||||||
VSLP | Slope compensation ramp | 520 | 620 | 720 | mV | |||
PWM | ||||||||
VVLY | Valley voltage | 1.2 | V | |||||
SOFT-START | ||||||||
VSS(ofst) | Offset voltage from SS pin to error amplifier input | 1 | V | |||||
RSS(chg) | Soft-start charge resistance | 320 | 430 | 600 | kΩ | |||
RSS(dchg) | Soft-start discharge resistance | 840 | 1200 | 1600 | ||||
ERROR AMPLIFIER | ||||||||
GBWP | Unity gain bandwidth product(1) | 1.5 | 3.0 | MHz | ||||
AOL | Open loop gain(1) | 60 | 80 | dB | ||||
IIB(FB) | Input bias current (current out of FB pin) | 100 | 300 | nA | ||||
ICOMP(src) | Output source current | VFB = 0.6 V, VCOMP = 1 V | 100 | 250 | μA | |||
ICOMP(snk) | Output sink current | VFB = 1.2 V, VCOMP = 1 V | 1.2 | 2.5 | mA | |||
OVERCURRENT PROTECTION | ||||||||
VISNS(oc) | Overcurrent detection threshold (at ISNS pin) | 4.5 ≤ VDD < 52 V, –40°C ≤ TJ ≤ 125°C | 120 | 150 | 180 | mV | ||
DOC | Overcurrent duty cycle(1) | 2% | ||||||
VSS(rst) | Overcurrent reset threshold voltage (at SS pin) | 100 | 150 | 350 | mV | |||
CURRENT-SENSE AMPLIFIER | ||||||||
ACS | Current sense amplifier gain | 4.2 | 5.6 | 7.2 | V/V | |||
IB(ISNS) | Input bias current | 1 | 3 | μA | ||||
DRIVER | ||||||||
IGDRV(src) | Gate driver source current | VGDRV = 4 V, TJ = 25°C | 375 | 400 | mA | |||
IGDRV(snk) | Gate driver sink current | VGDRV = 4 V, TJ = 25°C | 330 | 400 | ||||
LINEAR REGULATOR | ||||||||
VBP | Bypass voltage output | 0 mA < IBP < 15 mA | 7 | 8 | 9 | V | ||
DISABLE AND ENABLE | ||||||||
VDIS(en) | Turn-on voltage | 0.7 | 1.3 | V | ||||
VDIS(hys) | Hysteresis voltage | 25 | 130 | 220 | mV | |||
RDIS | DIS pin pulldown resistance | 0.7 | 1.1 | 1.5 | MΩ |