JAJSR90A September   2023  – July 2024 LMQ64480-Q1 , LMQ644A0-Q1 , LMQ644A2-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  Output Voltage Selection and Soft Start
      4. 7.3.4  SYNC Allows Clock Synchronization and Mode Selection
      5. 7.3.5  Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Power-Good Output Voltage Monitoring
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage and VCBOOT-UVLO (CB1 and CB2 Pin)
      10. 7.3.10 CONFIG Device Configuration Pin
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery From Dropout
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Hiccup
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Auto Mode Operation
          1. 7.4.3.2.1 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
        7. 7.4.3.7 Other Fault Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  BOOT Capacitor
        7. 8.2.2.7  VCC
        8. 8.2.2.8  CFF and RFF Selection
        9. 8.2.2.9  SYNCHRONIZATION AND MODE
        10. 8.2.2.10 External UVLO
        11. 8.2.2.11 Typical Thermal Performance
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.3 Output Voltage Selection and Soft Start

A voltage divider between the output voltage and the FB1 pin is used to create an adjustable output voltage from 0.8 to 20 V for the first buck converter. The thevenin impedance of the divider must be larger than 4 kohms, to correctly enter adjustable output voltage configuration. For lower output voltages a minimum of 10 kohms is recommended for RFBT to meet this requirement. For a fixed 5-V output connect FB1 to VCC through a 10 kohm resistor. For a fixed 3.3 V connect FB1 to AGND. For fixed output voltage configurations the first channel output voltage is sensed on pin 13 BIAS/VOSNS1.

For dual-output voltage configuration, RCONFIG = 0 (spread spectrum disabled) or 121 kΩ (spread spectrum enabled).

FB2 is configured in the same manner as FB1. A voltage divider between output voltage and the FB2 pin is used to create an adjustable output voltage from 0.8 to 20 V for the second buck converter. The thevenin impedance of the divider must be larger than 4 kohms, to correctly enter adjustable output voltage configuration. For lower output voltages a value of 10 kohms is recommended for RFBT to meet this requirement. For a fixed 5-V output, connect FB2 to VCC through a 10 kohm resistor. For a fixed 3.3 V connect FB2 to AGND. For fixed output voltage configurations, the second channel output voltage is sensed on pin 19. that is, VOSNS2.

Current sharing between multiple buck channels can increase the current. For one device, single-output multi-phase operation can double the single buck current and provide up to 12 A. Using three devices allows six times the current up to 36 A. When the device is configured to single-output multi-phase operation (9.53 kΩ < RCONFIG < 93.1kΩ) , FB2 is re-configured to provide an adjustable soft start (SS). An external capacitor can be placed from this pin to ground to extend the internal soft-start time. The time can be calculated using the soft-start current of 20 µA (typical) charging the external capacitor to the reference voltage of 0.8 V (typical). As an example, a 220-nF capacitor provides a soft start of 8 ms after the initialization of the device. The pin must also be tied to FB2/SS of all other LMQ stacked devices for fault communication between primary and secondary devices. Faults, such as thermal shutdown, are communicated by pulling the pin low and stops switching for all devices.

LMQ64480-Q1 LMQ644A0-Q1 LMQ644A2-Q1 Setting Output Voltage of Adjustable Versions Figure 7-3 Setting Output Voltage of Adjustable Versions

The LMQ644xx uses a 0.8-V reference. The following equation can be used to determine RFBB for a desired output voltage and a given RFBT. Usually, RFBT is limited to a maximum value of 100 kΩ to prevent drifting due to PCB leakage under harsh conditions. To improve light load efficiency, a larger resistance of up to 1 MΩ can be used in cleaner environments, or the fixed output voltage options can be used under harsher conditions.

Equation 3. R F B B k Ω = 0.8   × R F B T k Ω ( V O U T - 0.8 )

In addition, a feedforward capacitor CFF can be used to optimize the transient response. Typical values are provided in the applications section and were selected based upon the top feedback resistor to place a zero slightly above the cross-over frequency.