JAJSRL3 June   2024 THS6232

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12V
    6. 5.6 Electrical Characteristics VS = 40V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics VS = 12V
    9. 5.9 Typical Characteristics VS = 40V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4 Device Functional Modes

The THS6232 has five different functional modes set by the BIAS-1 and BIAS-2 pins. Table 6-1 shows the truth table for the device mode pin configuration and the associated description of each mode.

Table 6-1 BIAS-1 and BIAS-2 Logic Table
BIAS-1 BIAS-2 FUNCTION DESCRIPTION
0 0 Full-bias mode (100%) Amplifiers on with lowest distortion possible
1 0 Mid-bias mode (78%) Amplifiers on with power savings and a reduction in distortion performance
0 1 Low-bias mode (60%) Amplifiers on with enhanced power savings and a reduction of overall performance
0
(IADJ = float)		 1
(IADJ = float)		 Ultra-low-bias mode (40%) Amplifiers on with highest power savings and a reduction of overall performance
1 1 Shutdown mode Amplifiers off and output is high impedance

If the PLC application requires switching the line driver between all five power modes, and if the PLC application-specific integrated circuit (ASIC) has two control bits, then the two control bits can be connected to the bias pins BIAS-1 and BIAS-2 for switching between any of the five power modes. For the ultra-low-bias mode, float the IADJ pin to activate the mode. Most PLC applications, however, only require the line driver to switch between one active power mode and the shutdown mode. This type of 1-bit power mode control is illustrated in Figure 7-1, where the line driver can be switched between the full-bias and shutdown modes using just one control bit from the PLC ASIC.