JAJSRL3 June   2024 THS6232

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12V
    6. 5.6 Electrical Characteristics VS = 40V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics VS = 12V
    9. 5.9 Typical Characteristics VS = 40V
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Layout Guidelines

Achieving optimized performance with a high-frequency amplifier such as the THS6232 requires careful attention to board layout parasitic and external component types. The THS6222RHFEVM can be used as a reference when designing the circuit board. Recommendations that optimize performance include:

  1. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance, particularly on the output and inverting input pins, can cause instability; on the noninverting input, this capacitance can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, open a window around the signal I/O pins in all ground and power planes around these pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
  2. Minimize the distance (less than 0.25in, or 6.35mm) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout must not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Always decouple the power-supply connections with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves second-harmonic distortion performance. Use larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, on the main supply pins. These capacitors can be placed somewhat farther from the device and can be shared among several devices in the same area of the PCB.
  3. Careful selection and placement of external components preserves the high-frequency performance of the THS6232. Use very low reactance type resistors. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Although the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Place other network components, such as noninverting input termination resistors, close to the package. Where double-side component mounting is required, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value, as described in Section 7.2.1. Increasing the value reduces the bandwidth, whereas decreasing the value leads to a more peaked frequency response. The 1.24kΩ feedback resistor used in Section 5.8 is a good starting point for a gain of 10V/V design. For operation in ultra-low-bias mode, use a minimum 2kΩ feedback resistor for a device gain of 10V/V.
  4. Connections to other wide-band devices on the board can be made with short direct traces or through on board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Use relatively wide traces (50 mils to 100 mils, 0.050 inches to 0.100 inches, or 1.27mm to 2.54mm), preferably with ground and power planes opened up around them.
  5. Do not socket a high-speed part such as the THS6232. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, and can make achieving a smooth, stable frequency response almost impossible. Best results are obtained by soldering the THS6232 directly onto the board.
  6. Use the VS– plane to conduct the heat out of the package. The package attaches the die directly to an exposed thermal pad on the bottom, and must be soldered to the board. Electrically connect this pad to the same voltage plane as the most negative supply voltage (VS–) applied to the THS6232. Place as many vias as possible on the thermal pad connection and connect the vias to a heat spreading plane that is at the same potential as VS– on the bottom side of the PCB.