JAJSRS6A October   2023  – July 2024 MSPM0C1103-Q1 , MSPM0C1104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 ADC
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
      3. 7.11.3 Linearity Parameters
      4. 7.11.4 Typical Connection Diagram
    12. 7.12 Temperature Sensor
    13. 7.13 VREF
      1. 7.13.1 Voltage Characteristics
      2. 7.13.2 Electrical Characteristics
    14. 7.14 I2C
      1. 7.14.1 I2C Characteristics
      2. 7.14.2 I2C Filter
      3. 7.14.3 I2C Timing Diagram
    15. 7.15 SPI
      1. 7.15.1 SPI
      2. 7.15.2 SPI Timing Diagrams
    16. 7.16 UART
    17. 7.17 TIMx
    18. 7.18 Windowed Watchdog Characteristics
    19. 7.19 Emulation and Debug
      1. 7.19.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0C110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 CRC
    16. 8.16 UART
    17. 8.17 SPI
    18. 8.18 I2C
    19. 8.19 WWDT
    20. 8.20 Timers (TIMx)
    21. 8.21 Device Analog Connections
    22. 8.22 Input/Output Diagrams
    23. 8.23 Serial Wire Debug Interface
    24. 8.24 Device Factory Constants
    25. 8.25 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.15.1 SPI

over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SPI
fSPI SPI clock frequency Clock max speed = 24MHz
1.62 < VDD < 3.6V
Controller mode		 12 MHz
fSPI SPI clock frequency Clock max speed = 24MHz
1.62 < VDD < 3.6V
Peripheral mode		 12 MHz
DCSCK SCK Duty Cycle 40 50 60 %
Controller
tSCLK_H/L SCLK High or Low time  (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns
tCS.LEAD CS lead-time, CS active to clock 1 ns
tCS.LAG CS lag time, Last clock to CS inactive 11 ns
tCS.ACC CS access time, CS active to PICO data out 93 ns
tCS.DIS CS disable time, CS inactive to PICO high impedance 10 ns
tSU.CI POCI input data setup time (1) 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns
1.62 < VDD < 2.7V, delayed sampling enabled 1
tSU.CI POCI input data setup time (1) 2.7 < VDD < 3.6V, no delayed sampling 27 ns
 1.62 < VDD < 2.7V, no delayed sampling 35
tHD.CI POCI input data hold time 9 ns
tVALID.CO PICO output data valid time (2) 10 ns
tHD.CO PICO output data hold time (3) 1 ns
Peripheral
tCS.LEAD CS lead-time, CS active to clock 8 ns
tCS.LAG CS lag time, Last clock to CS inactive 0 ns
tCS.ACC CS access time, CS active to POCI data out 50 ns
tCS.DIS CS disable time, CS inactive to POCI high inpedance 50 ns
tSU.PI PICO input data setup time 2 ns
tHD.PI PICO input data hold time 1 ns
tVALID.PO POCI output data valid time(2) 2.7 < VDD < 3.6V 34 ns
tVALID.PO POCI output data valid time(2) 1.62 < VDD < 2.7V 41 ns
tHD.PO POCI output data hold time(3) 5 ns
(1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled.
(2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(3) Specifies how long data on the output is valid after the output changing SCLK clock edge