JAJSRW4 October   2024 AMC0386-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Digital Output
        1. 6.3.4.1 Output Behavior in Case of a Fullscale Input
        2. 6.3.4.2 Output Behavior in Case of a Missing High-Side Supply
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Best Design Practices
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

5.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VSNSP = –1 V to +1 V, and VSNSN = 0V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and fCLKIN = 10 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Input resistance AMC0386M04-Q1 TBD 8 TBD MΩ
AMC0386M06-Q1 TBD 10 TBD
AMC0386M10-Q1 TBD 12.5 TBD
Nominal resistive divider ratio VHVIN / VSNSP, AMC0386M04-Q1 401
VHVIN / VSNSP, AMC0386M06-Q1 601
VHVIN / VSNSP, AMC0386M10-Q1 1001
CMTI Common-mode transient immunity 100 V/ns
DC ACCURACY
EO Input offset error Referred to SNSP, TA = 25°C, HVIN = AGND –0.9 ±0.08 0.9 mV
Referred to HVIN, TA = 25°C, HVIN = AGND
AMC0386M04-Q1		 –360 ±30 200
Referred to HVIN, TA = 25°C, HVIN = AGND
AMC0386M06-Q1		 –540 ±50 300
Referred to HVIN, TA = 25°C, HVIN = AGND
AMC0386M10-Q1		 –900 ±80 900
TCEO Offset error temperature drift(3) Referred to SNSP, TA = 25°C, HVIN = AGND –0.004 ±0.0006 0.004 mV/°C
Referred to HVIN, HVIN = AGND
AMC0386M04-Q1		 –2.8 ±1.4 2.8
Referred to HVIN, HVIN = AGND
AMC0386M06-Q1		 –4.2 ±2.1 4.2
Referred to HVIN, HVIN = AGND
AMC0386M10-Q1		 –7 ±3.5 7
EG Gain error(1) TA = 25°C –0.25 ±0.02 0.25 %
TCEG Gain error temperature drift(4) –40 ±20 40 ppm/°C
INL Integral nonlinearity(2) Resolution: 16 bits –4 ±1.6 4 LSB
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
PSRR Power-supply rejection ratio(5) AVDD DC PSRR, HVIN = AGND,
AVDD from 3.0V to 5.5V		 83 dB
AVDD AC PSRR, HVIN = AGND,
AVDD with 10kHz / 100mV ripple		 83
AC ACCURACY
SNR Signal-to-noise ratio VSNSP = 2VPP, SNSN = AGND, fIN = 1kHz 86 89 dB
SINAD Signal-to-noise + distortion VSNSP = 2VPP, SNSN = AGND, fIN = 1kHz 76 86 dB
THD Total harmonic distortion VSNSP = 2VPP, SNSN = AGND, fIN = 1kHz –88 –77 dB
DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)
IIN Input current DGND ≤ VIN ≤ DVDD 7 µA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 x DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 x DVDD V
DIGITAL OUTPUT (CMOS)
CLOAD Output load capacitance fCLKIN = 10MHz 15 30 pF
VOH High-level output voltage IOH = –4mA DVDD – 0.4 V
VOL Low-level output voltage IOL = 4mA 0.4 V
POWER SUPPLY
IAVDD High-side supply current 5.3 7.5 mA
IDVDD Low-side supply current CLOAD = 15pF 3.6 5.1 mA
AVDDUV High-side undervoltage detection threshold AVDD rising 2.5 2.6 2.7 V
AVDD falling 1.9 2.0 2.1
DVDDUV Low-side undervoltage detection threshold DVDD rising 2.5 2.6 2.7 V
DVDD falling 1.9 2.0 2.1
(1) The typical value includes one sigma statistical variation.
(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(3) Offset error drift is calculated using the box method, as described by the following equation:
TCEO = (valueMAX - valueMIN) / TempRange
(4) Gain error drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((valueMAX - valueMIN) / (value x TempRange)) X 106
(5) This parameter is referred to SNSP.