JAJSRX9C January   2012  – November 2023 TPS40170-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  LDO Linear Regulators and Enable
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
      3. 6.3.3  Equations for Programming the Input UVLO
      4. 6.3.4  Overcurrent Protection and Short-Circuit Protection (OCP and SCP)
      5. 6.3.5  Oscillator and Voltage Feed-Forward
        1. 6.3.5.1 Calculating the Timing Resistance (RRT)
      6. 6.3.6  Feed-Forward Oscillator Timing Diagram
      7. 6.3.7  Soft-Start and Fault-Logic
        1. 6.3.7.1 Soft-Start During Overcurrent Fault
        2. 6.3.7.2 Equations for Soft-Start and Restart Time
      8. 6.3.8  Overtemperature Fault
      9. 6.3.9  Tracking
      10. 6.3.10 Adaptive Drivers
      11. 6.3.11 Start-Up Into Pre-Biased Output
      12. 6.3.12 31
      13. 6.3.13 Power Good (PGOOD)
      14. 6.3.14 PGND and AGND
      15. 6.3.15 Bootstrap Capacitor
      16. 6.3.16 Bypass and Filtering
    4. 6.4 Device Functional Modes
      1. 6.4.1 Frequency Synchronization
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Select A Switching Frequency
        2. 7.2.2.2  Inductor Selection (L1)
        3. 7.2.2.3  Output Capacitor Selection (C9)
        4. 7.2.2.4  Peak Current Rating of Inductor
        5. 7.2.2.5  Input Capacitor Selection (C1, C6)
        6. 7.2.2.6  MOSFET Switch Selection (Q1, Q2)
        7. 7.2.2.7  Timing Resistor (R7)
        8. 7.2.2.8  UVLO Programming Resistors (R2, R6)
        9. 7.2.2.9  Bootstrap Capacitor (C7)
        10. 7.2.2.10 VIN Bypass Capacitor (C18)
        11. 7.2.2.11 VBP Bypass Capacitor (C19)
        12. 7.2.2.12 SS Timing Capacitor (C15)
        13. 7.2.2.13 ILIM Resistor (R19, C17)
        14. 7.2.2.14 SCP Multiplier Selection (R5)
        15. 7.2.2.15 Feedback Divider (R10, R11)
        16. 7.2.2.16 Compensation: (R4, R13, C13, C14, C21)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bootstrap Resistor
      2. 7.3.2 SW-Node Snubber Capacitor
      3. 7.3.3 Input Resistor
      4. 7.3.4 LDRV Gate Capacitor
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MINMAXUNIT
Input voltageVIN–0.362V
M/S–0.3VIN
UVLO–0.316
SW–5VIN
BOOTVSW + 8.8
Output voltageHDRVVSWBOOTV
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW)–0.38.8
VBP, LDRV, COMP, RT, ENABLE, PGOOD, SYNC–0.38.8
VDD, FB, TRK, SS, ILIM–0.33.6
GroundingAGND-PGND, PGND-AGND200200mV
PowerPAD to AGND (must be electrically connected external to device)0
Ambient temperatureTA–40125°C
Storage temperatureTstg–55150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.