JAJSS82E August   2009  – July 2024 LPV521

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input Stage
      2. 6.4.2 Output Stage
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Capacitive Load
      2. 7.1.2 EMI Suppression
    2. 7.2 Typical Applications
      1. 7.2.1 60Hz Twin T-Notch Filter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Portable Gas Detection Sensor
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 High-Side Battery Current Sensing
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at TA = 25°C, V+ = 1.8V, 3.3V, and 5V, V– = 0V, VCM = VO = VS / 2, and RL > 1 MΩ (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– + 0.3V –1 0.1 1 mV
TA = –40°C to +125°C –1.23 1.23
VCM = V+ – 0.3V –1 0.1 1
TA = –40°C to +125°C –1.23 1.23
TCVOS Input offset voltage drift(2) ±0.4 µV/°C
TA = –40°C to +125°C V+ = 1.8V, 3.3V –3 3
V+ = 5V –3.5 3.5
PSRR Power-supply rejection ratio 1.6V ≤ V+ ≤ 5.5V,
VCM = 0.3V		 85 109 dB
TA = –40°C to +125°C 76
INPUT BIAS CURRENT
IBIAS Input bias current V+ = 1.8V, 3.3V –1 0.01 1 pA
V+ = 5V –1 0.04 1
TA = –40°C to +125°C –50 +50
IOS Input offset current V+ = 1.8V 10 fA
V+ = 3.3V 20
V+ = 5V 60
NOISE
Input-referred voltage noise V+ = 1.8V 24 µVPP
V+ = 3.3V, 5V 22
en Input-referred voltage noise density  f = 100Hz V+ = 1.8V 265 nV/√Hz
V+ = 3.3V 259
V+ = 5V 255
in Input-referred current noise  f = 100Hz 100 fA/√Hz
INPUT VOLTAGE
CMRR Common-mode rejection ratio V– ≤ VCM ≤ V+ V+ = 1.8V 66 92 dB
V+ = 1.8V, TA = –40°C to +125°C 60
V+ = 3.3V 72 97
V+ = 3.3V, TA = –40°C to +125°C 70
V+ = 5V 75 102
V+ = 5V, TA = –40°C to +125°C 74
V– ≤ VCM ≤ V+ – 1.1V V+ = 1.8V 75 101
V+ = 1.8V, TA = –40°C to +125°C 74
V+ = 3.3V 78 106
V+ = 3.3V, TA = –40°C to +125°C 75
V+ = 5V 84 108
V+ = 5V, TA = –40°C to +125°C 80
V+ – 0.6V ≤ VCM ≤ V+ V+ = 1.8V 75 120
V+ = 1.8V, TA = –40°C to +125°C 53
V+ = 3.3V 77 121
V+ = 3.3V, TA = –40°C to +125°C 76
V+ = 5V 77 115
V+ = 5V, TA = –40°C to +125°C 76
CMVR Common-mode voltage range V+ = 1.8V, CMRR ≥ 67dB,
V+ = 3.3V, CMRR ≥ 72dB,
V+ = 5V, CMRR ≥ 75dB		 (V–) – 0.1 (V+) + 0.1 V
TA = –40°C to +125°C,
V+ = 1.8V, CMRR ≥ 60dB,
V+ = 3.3V, CMRR ≥ 70dB,
V+ = 5V, CMRR ≥ 74dB		 (V–) (V+) V
OPEN-LOOP GAIN
AVOL Large-signal voltage gain V– + 0.5V ≤ VO ≤ V+ – 0.5V,
RL = 100kΩ to V+/2		 V+ = 1.8V 74 125 dB
V+ = 1.8V, TA = –40°C to +125°C 73
V+ = 3.3V 82 120
V+ = 3.3V, TA = –40°C to +125°C 76
V+ = 5V 84 132
V+ = 5V, TA = –40°C to +125°C 76
FREQUENCY RESPONSE
GBW Gain bandwidth product CL = 20pF, RL = 100kΩ V+ = 1.8V 6.1 kHz
V+ = 3.3V, 5V 6.2
SR Slew rate Falling edge, AV = +1,
VIN = V+ to V–		 V+ = 1.8V 2.9 V/ms
V+ = 3.3V 2.9
V+ = 5V 1.1 2.7
V+ = 5V, TA = –40°C to +125°C 1.2
Rising edge, AV = +1,
VIN = V– to V+		 V+ = 1.8V 2.3
V+ = 3.3V 2.5
V+ = 5V 1.1 2.4
V+ = 5V, TA = –40°C to +125°C 1.2
θm Phase margin CL = 20pF, RL = 100kΩ V+ = 1.8V 72 deg
V+ = 3.3V, 5V 73
Gm Gain margin CL = 20pF, RL = 100kΩ V+ = 1.8V, 3.3V 19 dB
V+ = 5V 20
OUTPUT
VO Output voltage Swing from positive rail,
RL = 100kΩ to V+/2,
VIN(diff) = 100mV		 V+ = 1.8V 2 50 mV
V+ = 1.8V, TA = –40°C to +125°C 50
V+ = 3.3V 3 50
V+ = 3.3V, TA = –40°C to +125°C 50
V+ = 5V 3 50
V+ = 5V, TA = –40°C to +125°C 50
Swing from negative rail,
RL = 100kΩ to V+/2,
VIN(diff) = –100mV		 V+ = 1.8V 2 50
V+ = 1.8V, TA = –40°C to +125°C 50
V+ = 3.3V 2 50
V+ = 3.3V, TA = –40°C to +125°C 50
V+ = 5V 3 50
V+ = 5V, TA = –40°C to +125°C 50
IO Output current(3) Sourcing, VO to V–,
VIN(diff) = 100mV		 V+ = 1.8V 1 3 mA
V+ = 1.8V, TA = –40°C to +125°C 0.5
V+ = 3.3V 5 11
V+ = 3.3V, TA = –40°C to +125°C 4
V+ = 5V 15 23
V+ = 5V, TA = –40°C to +125°C 8
Sinking, VO to V+,
VIN(diff) = –100mV		 V+ = 1.8V 1 3
V+ = 1.8V, TA = –40°C to +125°C 0.5
V+ = 3.3V 5 12
V+ = 3.3V, TA = –40°C to +125°C 4
V+ = 5V 15 22
V+ = 5V, TA = –40°C to +125°C 8
POWER SUPPLY
IS Supply current VCM = V– + 0.3 V V+ = 1.8V 345 400 nA
V+ = 1.8V, TA = –40°C to +125°C 580 nA
V+ = 3.3V 346 400 nA
V+ = 3.3V, TA = –40°C to +125°C 600 nA
V+ = 5V 351 400 nA
V+ = 5V, TA = –40°C to +125°C 620 nA
VCM = V+ – 0.3 V V+ = 1.8V 472 600 nA
V+ = 1.8V, TA = –40°C to +125°C 850 nA
V+ = 3.3V 471 600 nA
V+ = 3.3V, TA = –40°C to +125°C 860 nA
V+ = 5V 475 600 nA
V+ = 5V, TA = –40°C to +125°C 870 nA
NOISE IMMUNITY
EMIRR EMI rejection ratio,
IN+ and IN– (4)		 V+ = 5V,
VRF_PEAK = 100mVP (–20dBP)		 f = 400MHz 121 dB
f = 900MHz 121
f = 1800MHz 124
f = 2400MHz 142
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No min and max specifications of parametric performance are indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. 
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
(3) The short circuit test is a momentary open-loop test.
(4) The EMI rejection ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS).