The most used thermal resistance parameter R_θJA is highly dependent on the heat-spreading capability built into the particular PCB design. Therefore, R_θJA varies according to the total copper area, copper weight, and location of the planes. The R_θJA recorded in the Thermal Information table is determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area. R_θJA is only used as a relative measure of package thermal performance. For a well-designed thermal layout, R_θJA is actually the sum of R_θJCbot plus the thermal resistance contribution by the PCB copper. R_θJCbot is the package junction-to-case (bottom) thermal resistance.

Figure 8-2 and Figure 8-3 show the functions of R_θJA and ψ_JB versus copper area and thickness. These plots are generated with a 101.6mm × 101.6mm × 1.6mm PCB of two and four layers. For the 4-layer board, inner planes use 1oz copper thickness. Outer layers are simulated with both 1oz and 2oz copper thickness. A 3×4 (KVU package) array of thermal vias with a 300µm drill diameter and 25µm copper plating is located beneath the device thermal pad. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.