JAJST23 June 2024 BQ41Z50
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SMBus 100kHz | ||||||
fSMB | SMBus operating frequency | TARGET mode, SMBC 50% duty cycle | 10 | 100 | kHz | |
fMAS | SMBus host clock frequency | 10 | 100 | kHz | ||
tBUF | Bus free time between start and stop | 4.7 | µs | |||
tHD:START | Hold time after (repeated) start | 4 | µs | |||
tSU:START | Repeated start setup time | 4.7 | µs | |||
tSU:STOP | Stop setup time | 4 | µs | |||
tHD:DATA | Data hold time | 0 | ns | |||
tSU:DATA | Data setup time | 250 | ns | |||
tTIMEOUT | Error signal detect time | 25 | 35 | ms | ||
tLOW | Clock low period | 4.7 | µs | |||
tHIGH | Clock high period | 4 | 50 | µs | ||
tLOW(SEXT) | Cumulative clock low target extend time | 25 | ms | |||
tLOW(MEXT) | Cumulative clock low host extend time | 10 | ms | |||
tF | Clock fall time | VIH(MIN) + 0.15 to VIL(MAX) – 0.15 | 300 | ns | ||
tR | Clock rise time | VIL(MAX) – 0.15 to VIH(MIN) + 0.15 | 1000 | ns | ||
tBUSLO | Max SMBC/SMBD Low (BUSLO) Signal Detect Time by device | BLTx = 0x1 to 0x7 | 0.5 | 3.5 | s | |
ΔtBUSLO | BUSLO detect time program step | 0.5 | s | |||
CD | Capacitive load for each bus line | 400 | pF | |||
SMBus 400kHz | ||||||
fSMB | SMBus operating frequency | TARGET mode, SMBC 50% duty cycle | 10 | 400 | kHz | |
fMAS | SMBus host clock frequency | 10 | 400 | kHz | ||
tBUF | Bus free time between start and stop | 1.3 | µs | |||
tHD:START | Hold time after (repeated) start | 0.6 | µs | |||
tSU:START | Repeated start setup time | 0.6 | µs | |||
tSU:STOP | Stop setup time | 0.6 | µs | |||
tHD:DATA | Data hold time | 0 | ns | |||
tSU:DATA | Data setup time | 100 | ns | |||
tTIMEOUT | Error signal detect time | 25 | 35 | ms | ||
tLOW | Clock low period | 1.3 | µs | |||
tHIGH | Clock high period | 0.6 | 50 | µs | ||
tLOW(SEXT) | Cumulative clock low target extend time | 25 | ms | |||
tLOW(MEXT) | Cumulative clock low host extend time | 10 | ms | |||
tF | Clock fall time | VIH(MIN) + 0.15 to VIL(MAX) – 0.15 | 300 | ns | ||
tR | Clock rise time | VIL(MAX) – 0.15 to VIH(MIN) + 0.15 | 300 | ns | ||
tBUSLO | Max SMBC/SMBD Low (BUSLO) Signal Detect Time by device | BLTx = 0x1 to 0x7 | 0.5 | 3.5 | s | |
ΔtBUSLO | BUSLO detect time program step | 0.5 | s | |||
CD | Capacitive load for each bus line | 400 | pF | |||
SMBus 1MHz | ||||||
fSMB | SMBus operating frequency | TARGET mode, SMBC 50% duty cycle | 10 | 1000 | kHz | |
fMAS | SMBus host clock frequency | 10 | 1000 | kHz | ||
tBUF | Bus free time between start and stop | 0.5 | µs | |||
tHD:START | Hold time after (repeated) start | 0.26 | µs | |||
tSU:START | Repeated start setup time | 0.26 | µs | |||
tSU:STOP | Stop setup time | 0.26 | µs | |||
tHD:DATA | Data hold time | 0 | ns | |||
tSU:DATA | Data setup time | 50 | ns | |||
tTIMEOUT | Error signal detect time | 25 | 35 | ms | ||
tLOW | Clock low period | 0.5 | µs | |||
tHIGH | Clock high period | 0.26 | 50 | µs | ||
tLOW(SEXT) | Cumulative clock low target extend time | 25 | ms | |||
tLOW(MEXT) | Cumulative clock low host extend time | 10 | ms | |||
tF | Clock fall time | VIH(MIN) + 0.15 to VIL(MAX) – 0.15 | 120 | ns | ||
tR | Clock rise time | VIL(MAX) – 0.15 to VIH(MIN) + 0.15 | 120 | ns | ||
tBUSLO | Max SMBC/SMBD Low (BUSLO) Signal Detect Time by device | BLTx = 0x1 to 0x7 | 0.5 | 3.5 | s | |
ΔtBUSLO | BUSLO detect time program step | 0.5 | s | |||
CD | Capacitive load for each bus line | 100 | pF |