JAJST23 June   2024 BQ41Z50

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Equivalent Diagrams
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Power Supply Control
    7. 6.7  Current Wake Detector
    8. 6.8  VC0, VC1, VC2, VC3, VC4, PACK
    9. 6.9  SMBD, SMBC
    10. 6.10 PRES/SHUTDN, DISP
    11. 6.11 ALERT
    12. 6.12 Coulomb Counter Digital Filter (CC1)
    13. 6.13 ADC Digital Filter
    14. 6.14 CHG, DSG High-side NFET Drivers
    15. 6.15 Precharge (PCHG) FET Drive
    16. 6.16 FUSE Drive
    17. 6.17 Internal Temperature Sensor
    18. 6.18 TS1, TS2, TS3, TS4
    19. 6.19 Flash Memory
    20. 6.20 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7
    21. 6.21 Elliptical Curve Cryptography (ECC)
    22. 6.22 SMBus Interface Timing
    23. 6.23 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Primary (1st Level) Safety Features
      2. 7.3.2 Secondary (2nd Level) Safety Features
      3. 7.3.3 Charge Control Features
      4. 7.3.4 Gas Gauging
      5. 7.3.5 Lifetime Data Logging Features
      6. 7.3.6 Authentication
      7. 7.3.7 Configuration
        1. 7.3.7.1 Oscillator Function
        2. 7.3.7.2 Real Time Clock
        3. 7.3.7.3 System Present Operation
        4. 7.3.7.4 Emergency Shutdown
        5. 7.3.7.5 2-Series, 3-Series, or 4-Series Cell Configuration
        6. 7.3.7.6 Cell Balancing
        7. 7.3.7.7 LED Display
      8. 7.3.8 Battery Parameter Measurements
        1. 7.3.8.1 Charge and Discharge Counting
        2. 7.3.8.2 Voltage
        3. 7.3.8.3 Current
        4. 7.3.8.4 Temperature
        5. 7.3.8.5 Communications
          1. 7.3.8.5.1 SMBus On and Off State
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Current Path
          1. 8.2.2.1.1 Protection FETs
          2. 8.2.2.1.2 Chemical Fuse
          3. 8.2.2.1.3 Lithium-Ion Cell Connections
          4. 8.2.2.1.4 Sense Resistor
          5. 8.2.2.1.5 ESD Mitigation
        2. 8.2.2.2 Gas Gauge Circuit
          1. 8.2.2.2.1 Coulomb-Counting Interface
          2. 8.2.2.2.2 Low-dropout Regulators (LDOs)
            1. 8.2.2.2.2.1 REG18
            2. 8.2.2.2.2.2 REG135
          3. 8.2.2.2.3 System Present
          4. 8.2.2.2.4 SMBus Communication
          5. 8.2.2.2.5 FUSE Circuitry
        3. 8.2.2.3 Secondary-Current Protection
          1. 8.2.2.3.1 Cell and Battery Inputs
          2. 8.2.2.3.2 External Cell Balancing
          3. 8.2.2.3.3 PACK and FET Control
          4. 8.2.2.3.4 Temperature Measurement
          5. 8.2.2.3.5 LEDs
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
        2. 8.4.1.2 ESD Spark Gap
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.20 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7

Typical values stated where TA = 25°C and VBAT = 14.4V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 3.0V to 28V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
GPIO1, GPIO2
VIN Input voltage range GPIO1, GPIO2 –0.2 VREG18 V
VIH High-level input voltage GPIO1, GPIO2 0.7 x VREG18 V
VIL Low-level input voltage GPIO1, GPIO2 0.3 x VREG18 V
VIOHYS(1) Hysteresis of Input GPIO1, GPIO2 75 mV
VOH Output voltage high GPIO1, GPIO2: IOH = –450µA 0.85 × VREG18 V
VOL Output voltage low GPIO1, GPIO2: IOH = 1mA 0.35 V
tPWMRISE PWM Output Rise Time GPIO2: CL = 100pF, Qtot = 1nC, 0% to 90% of Gate Drive, PWM_SYNC = 1 6 µs
tPWMFALL PWM Output Fall Time GPIO2: CL = 100pF, Qtot = 1nC, 100% to 10% of Gate Drive, PWM_SYNC = 1 6 µs
RPD Internal pull-down resistance GPIO1, GPIO2 15 20 30 kΩ
RPU Internal pull-up resistance GPIO1, GPIO2 15 20 30 kΩ
CI(1) Input capacitance GPIO1, GPIO2 1.5 pF
Ilkg(1) Input leakage current GPIO1, GPIO2 1 2 µA
GPIO3
VIN Input voltage range GPIO3 –0.2 5.5 V
VIH High-level input voltage GPIO3 0.7 x VREG18 V
VIL Low-level input voltage GPIO3 0.3 x VREG18 V
VIOHYS(1) Hysteresis of Input GPIO3 75 mV
VOL Output voltage low GPIO3: IOH = 3mA 0.35 V
RBUS_PD Internal weak pull-down resistance GPIO3, Always ON 1 3 5 MΩ
RPD Internal pull-down resistance GPIO3 35 40 50 kΩ
CI (1) Input capacitance GPIO3 1.8 pF
Ilkg(1) Input leakage current GPIO3, including always on RBUS_PD pull-down 0.5 2 µA
GPIO4, GPIO5, GPIO6, GPIO7 (GPIO mode enabled, LED mode disabled)
VIN Input voltage range Internal weak pull-up disabled –0.2 5.5 V
Internal weak pull-up enabled –0.2 VREG18
VIH High-level input voltage GPIO4, GPIO5, GPIO6, GPIO7 0.7 × VREG18 V
VIL Low-level input voltage GPIO4, GPIO5, GPIO6, GPIO7 0.3 x VREG18 V
VIOHYS(1) Hysteresis of Input GPIO4, GPIO5, GPIO6, GPIO7 75 mV
VOH Output voltage high GPIO4, GPIO5, GPIO6, GPIO7: IOH = –1mA 0.7 × VREG18 V
VOL Output voltage low GPIO4, GPIO5, GPIO6, GPIO7: IOL = 3mA 0.3 × VREG18 V
RWKPD Internal weak pull-down resistance GPIO4, GPIO5, GPIO6, GPIO7 0.8 1 1.2 MΩ
RWKPU Internal weak pull-up resistance GPIO4, GPIO5, GPIO6, GPIO7 0.8 1 1.2 MΩ
CI (1) Input capacitance GPIO4, GPIO5, GPIO6, GPIO7 5 pF
Ilkg(1) Input leakage current GPIO4, GPIO5, GPIO6, GPIO7 1 2 µA
(1) Specified by design. Not production tested