JAJST23 June 2024 BQ41Z50
ADVANCE INFORMATION
The PACK and VCC inputs provide power to the BQ41Z50 from the charger. The PACK input also provides a method to measure and detect the presence of a charger.
The N-channel charge and discharge FETs are controlled with 5.1kΩ series gate resistors, which provide a switching time constant of a few microseconds. The 10MΩ resistors ensure that the FETs are off in the event of an open connection to the FET drivers.
Q4 is provided to protect the discharge FET (Q3) in the event of a reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the PACK+ input becomes slightly negative. Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002 from the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor.
The BQ41Z50 device has the capability to provide a current-limited charging path typically used for low battery voltage or low temperature charging. The BQ41Z50 device uses an external P-channel, precharge FET (Q1) controlled by PCHG.