JAJSTF3U
January 1993 – July 2024
SN54LVC00A
,
SN54LVC00A-SP
,
SN74LVC00A
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions, SN54LVC00A
5.4
Recommended Operating Conditions, SN74LVC00A
5.5
Thermal Information
5.6
Electrical Characteristics, SN54LVC00A
5.7
Electrical Characteristics, SN74LVC00A
5.8
Switching Characteristics, SN54LVC00A
5.9
Switching Characteristics, SN74LVC00A
5.10
Operating Characteristics
5.11
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced High-Drive CMOS Push-Pull Outputs
7.3.2
Standard CMOS Inputs
7.3.3
Clamp Diodes
7.3.4
Over-voltage Tolerant Inputs
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
Power Supply Recommendations
8.3
Layout
8.3.1
Layout Guidelines
8.3.2
Layout Example
9
Device and Documentation Support
9.1
Related Links
9.2
Receiving Notification of Documentation Updates
9.3
サポート・リソース
9.3.1
Community Resources
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
46
11
Mechanical, Packaging, and Orderable Information
8.2.2
Detailed Design Procedure
Recommended Input Conditions
Rise time and fall time specs: See (Δt/ΔV) in the
Section 5.4
table.
Specified high and low levels: See (V
IH
and V
IL
) in the
Section 5.4
table.
Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid V
CC
.
Recommended Output Conditions
Load currents should not exceed 25 mA per output and 50 mA total for the part.
Outputs should not be pulled above 5.5 V.