JAJSUK6A May 2024 – October 2024 MSPM0L1227 , MSPM0L1228 , MSPM0L2227 , MSPM0L2228
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
fADCCLK | ADC clock frequency | 4 | 32 | MHz | |||
tADC trigger | Software trigger minimum width | 3 | ADCCLK cycles | ||||
tSample | Sampling time | 12-bit mode, RS = 50Ω, Cpext = 10pF | 156 | ns | |||
tSample_VREF | Sample time with VREF | ADC CHANNEL=28,12-bit mode,VDD as reference | 4 | µs | |||
tSample_SupplyMon(VDD) | Sample time with Supply Monitor (VDD/3)(1) | 5 | µs | ||||
tSample_SupplyMon(VBAT) | Sample time with Supply Monitor (VBAT/3)(1) | 5 | µs |