JAJSV03 July   2024 TCAN1473-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings - IEC Specifications
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation Ratings
    7. 5.7  Power Supply Characteristics
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Signal Improvement
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Pins
        1. 7.3.1.1 VSUP Pin
        2. 7.3.1.2 VCC Pin
        3. 7.3.1.3 VIO Pin
      2. 7.3.2 Digital Inputs and Outputs
        1. 7.3.2.1 TXD Pin
        2. 7.3.2.2 RXD Pin
        3. 7.3.2.3 nFAULT Pin
        4. 7.3.2.4 EN Pin
        5. 7.3.2.5 nSTB Pin
      3. 7.3.3 GND
      4. 7.3.4 INH Pin
      5. 7.3.5 WAKE Pin
      6. 7.3.6 CAN Bus Pins
      7. 7.3.7 Faults
        1. 7.3.7.1 Internal and External Fault Indicators
          1. 7.3.7.1.1 Power-Up (PWRON Flag)
          2. 7.3.7.1.2 Wake-Up Request (WAKERQ Flag)
          3. 7.3.7.1.3 Undervoltage Faults
            1. 7.3.7.1.3.1 Undervoltage on VSUP
            2. 7.3.7.1.3.2 Undervoltage on VCC
            3. 7.3.7.1.3.3 Undervoltage on VIO
          4. 7.3.7.1.4 CAN Bus Fault (CBF Flag)
          5. 7.3.7.1.5 TXD Dominant State Timeout (TXDDTO Flag)
          6. 7.3.7.1.6 TXD Shorted to RXD Fault (TXDRXD Flag)
          7. 7.3.7.1.7 CAN Bus Dominant Fault (CANDOM Flag)
      8. 7.3.8 Local Faults
        1. 7.3.8.1 TXD Dominant Timeout (TXD DTO)
        2. 7.3.8.2 Thermal Shutdown (TSD)
        3. 7.3.8.3 Undervoltage Lockout (UVLO)
        4. 7.3.8.4 Unpowered Devices
        5. 7.3.8.5 Floating Terminals
        6. 7.3.8.6 CAN Bus Short-Circuit Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Mode Description
        1. 7.4.1.1 Normal Mode
        2. 7.4.1.2 Silent Mode
        3. 7.4.1.3 Standby Mode
        4. 7.4.1.4 Go-To-Sleep Mode
        5. 7.4.1.5 Sleep Mode
          1. 7.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 7.4.1.5.2 Local Wake-Up (LWU) via WAKE Input Terminal
      2. 7.4.2 CAN Transceiver
        1. 7.4.2.1 CAN Transceiver Operation
          1. 7.4.2.1.1 CAN Transceiver Modes
            1. 7.4.2.1.1.1 CAN Off Mode
            2. 7.4.2.1.1.2 CAN Autonomous: Inactive and Active
            3. 7.4.2.1.1.3 CAN Active
          2. 7.4.2.1.2 Driver and Receiver Function Tables
          3. 7.4.2.1.3 CAN Bus States
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Design Requirements
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
      3. 8.1.3 Detailed Design Procedure
        1. 8.1.3.1 CAN Termination
      4. 8.1.4 Application Curves
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
      1. 11.1.1 Packaging Information
      2. 11.1.2 Tape and Reel Information

5.10 Switching Characteristics

Over recommended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12 V, VIO = 3.3 V, VCC = 5 V and RL = 60 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver Characteristics
tprop(TxD-busdom) Propagation delay time, high-to-low TXD edge to bus dominant (recessive to dominant)
RL = 60 Ω, CL = 100 pF, RCM = open
See  Figure 6-4		 80 ns
tprop(TxD-busrec) Propagation delay time, low-to-high TXD edge to bus recessive (dominant to recessive) 80 ns
tsk(p) Pulse skew (|tprop(TxD-busdom) - tprop(TxD-busrec)|) RL = 60 Ω, CL = 100 pF, RCM = open
See Figure 6-4		 3 ns
tR Differential output signal rise time 25 ns
tF Differential output signal fall time 25 ns
tTXDDTO Dominant timeout TXD = 0 V, RL = 60 Ω, CL = open
See Figure 6-7		 1.2 3.8 ms
Receiver Characteristics
tprop(busdom-RxD) Propagation delay time, bus dominant input to RxD low output
CL(RXD) = 15 pF
See Figure 6-5		 110 ns
tprop(busrec-RxD) Propagation delay time, bus to recessive input to RXD high output 110 ns
tR Output signal rise time (RXD) CL(RXD) = 15 pF
See Figure 6-5		 3 ns
tF Output signal fall time (RXD) 3 ns
tBUSDOM Dominant time out RL = 60 Ω, CL = open
See Figure 6-7		 1.4 3.8 ms
CAN FD Signal Improvement Characteristics
tPAS_REC_START Start time of passive recessive phase RL = 45 to 65 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
Measured from rising TXD edge with < 5ns slope at 50% threshold, to the end of the signal improvement phase;
RDIFF_PAS_REC ≥ MIN RDIFF_ACT_REC;
RSE_CANH/L ≥ MIN RSE_SIC_REC		 530 ns
tSIC_START Start time of active signal improvement phase RL = 45 to 65 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
Measured from rising TXD edge with < 5ns slope at 50% threshold to the start of active signal improvement phase
 		 120 ns
tSIC_END End time of active signal improvement phase RL = 45 to 65 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
Measured from rising TXD edge with < 5ns slope at 50% threshold to the end of active signal improvement phase
 		 355 ns
tΔBit(Bus) Transmitted bit width variation Bus recessive bit length variation relative to TxD bit length, see Figure 6-6 tΔBit(Bus) = tBit(Bus) - tBit(TxD) , tBit(TxD) >= 200 ns
RL = 45 to 65 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF		 –10 10 ns
tΔBit(RxD) Received bit width variation RxD recessive bit length variation relative to TXD bit length, see Figure 6-6 tΔBit(RxD) = tBit(RxD) - tBit(TxD) , tBit(TxD) >= 200 ns
RL = 45 to 65 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF		 –30 20 ns
tΔREC Receiver timing symmetry RXD recessive bit length variation relative to bus bit length, see Figure 6-6 tΔREC = tBit(RxD) - tBit(Bus) , tBit(TxD) >= 200 ns
RL = 45 to 65 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF		 –20 15 ns