JAJSVH2 October   2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 6.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 6.10 Timing Requirements
    11. 6.11 Output Interface Timing Diagram
    12. 6.12 Typical Characteristics: 25MSPS
    13. 6.13 Typical Characteristics - 65MSPS
    14. 6.14 Typical Characteristics - 125MSPS
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Single Ended Input
        2. 7.3.1.2 Differential Input
        3. 7.3.1.3 Analog Input Bandwidth
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Digital Interface
        1. 7.3.3.1 Test Pattern
        2. 7.3.3.2 Interface Configuration using Pin Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down
  9. 8 Application Information Disclaimer
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Input Signal Path
        2. 8.1.2.2 Sampling Clock
      3. 8.1.3 Application Curves
    2. 8.2 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.10 Timing Requirements

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC TIMING SPECIFICATIONS
tAD Aperture Delay 0.5 ns
tA Aperture Jitter square wave clock with fast edges 250 fs
tACQ Signal acquisition period, referenced to sampling clock falling edge
-TS/5
 		 Sampling Clock Period
tCONV Signal conversion period, referenced to sampling clock falling edge Fs = 25 MSPS 5.5 ns
Fs = 65 MSPS 5.5 ns
Fs = 125 MSPS 5.5 ns
Wake up time Time to valid data after coming out of power down. Internal reference. 30 us
ADC Latency Signal input to data output DDR 1 ADC clock cycles
SDR 1
INTERFACE TIMING - DDR CMOS
tPD Propagation delay: sampling clock falling edge to DCLK rising edge TS/4 + 3 ns
tDE DCLK edge to previous data transition Fs = 25 MSPS -10 -9 ns
Fs = 65 MSPS -3.8 -3.4
Fs = 125 MSPS -2 -1.8
tDL DCLK edge to next data transition Fs = 25 MSPS 9 10
Fs = 65 MSPS 3.4 3.8
Fs = 125 MSPS 1.8 2
INTERFACE TIMING - SDR CMOS
tPD Propagation delay: sampling clock falling edge to DCLK rising edge TS/4 + 3 ns
tDE DCLK edge to previous data transition Fs = 25 MSPS -20 -18 ns
Fs = 65 MSPS -7.6 -6.9
Fs = 125 MSPS -4 -3.6
tDV DCLK edge to next data transition Fs = 25 MSPS 18 20
Fs = 65 MSPS 6.9 7.7
Fs = 125 MSPS 3.6 4