JAJSVH7A October   2024  – November 2024 TPS61287

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Start-up
      2. 6.3.2 Undervoltage Lockout (UVLO)
      3. 6.3.3 Programmable EN/UVLO
      4. 6.3.4 Switching Valley Current Limit
      5. 6.3.5 External Clock Synchronization
      6. 6.3.6 Stackable Multi-phase Operation
      7. 6.3.7 Device Functional Modes
        1. 6.3.7.1 Forced PWM Mode
        2. 6.3.7.2 Auto PFM Mode
      8. 6.3.8 Overvoltage Protection
      9. 6.3.9 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting Output Voltage
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Bootstrap And VCC Capacitors Selection
        4. 7.2.2.4 MOSFET Selection
        5. 7.2.2.5 Input Capacitor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPS61287 14-Pin RZP VQFN Package (Top View) Figure 4-1 14-Pin RZP VQFN Package (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NUMBER
ILIM 1 I Programmable switching valley current limit. An external resistor must be connected between this pin and the AGND pin.
FB 2 I Output voltage feedback pin. Connect to the center tap of a resistor divider to program the output voltage.
COMP 3 O Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin.
MODE 4 I Operating mode selection pin at light load condition, this pin must not be floating.

MODE = logic high, Forced PWM mode.

MODE = logic low, Auto PFM mode.
VOUT 5 P Boost converter output.
SW 6 P The switching node pin. This pin is connected to the drain of the external low-side MOSFET and the source of the internal high-side MOSFET.
BOOT 7 O Power supply for the high-side MOSFET gate driver. A ceramic capacitor of 0.1μF to 1.0μF must be connected between this pin and the SW pin.
PGND 8 G Power ground of external low side MOSFET. Source of external low side MOSFET must be connected to this pin.
DRV 9 O Gate driver output for external low-side MOSFET.
M/SYNC 10 I When the M/SYNC pin is short to ground , the device works with internal configured switching frequency. When a valid clock signal is applied to this pin, the switching frequency of the device is forced to the external clock.
VCC 11 O Output of the internal regulator. A ceramic capacitor of more than 2.2µF is required between this pin and AGND.
VIN 12 I IC power supply input .
EN/UVLO 13 I Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and puts the device into shutdown mode. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider. This pin must not be left floating and must be terminated.
AGND 14 G Analog signal ground.
(1) I = Input, O = Output, G = Ground, P = Power.