JAJSVL9 November   2024 UCC33421-Q1

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Safety-Related Certifications
    7. 6.7 Electrical Characteristics
    8. 6.8 External BOM Components
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 Output Voltage Soft-Start
      3. 7.3.3 Output Voltage Steady-State Regulation
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Input Under-voltage and Over-Voltage Lockout
        2. 7.3.4.2 Output Under-Voltage Protection
        3. 7.3.4.3 Output Over-Voltage Protection
        4. 7.3.4.4 Over-Temperature Protection
        5. 7.3.4.5 Fault Reporting and Auto-Restart
      5. 7.3.5 VCC Load Recommended Operating Area
      6. 7.3.6 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical and Packaging Information

Design Requirements

To design using UCC33421-Q1, a few simple design considerations must be evaluated. Table 8-1 shows some recommended values for a typical application. See Section 8.3 and Section 8.4 sections to review other key design considerations for the UCC33421-Q1.

Table 8-1 Design Parameters
PARAMETER RECOMMENDED VALUE
Input supply voltage, VINP 4.5V to 5.5V
First Decoupling capacitance between VINP and GNDP 15nF, 50V, ± 10%, X7R
Second Decoupling capacitance between VINP and GNDP 10µF, 10V, X7R
First Decoupling capacitance between VCC and GNDS 15nF, 50V, ± 10%, X7R
Second Decoupling capacitance between VCC and GNDS 22µF, 10V, X7R
EN/FLT pin resistor for fault reporting 18kΩ