JAJU835 December   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
      1.      10
    2. 2.2 Highlighted Products
      1. 2.2.1 DRV5056
      2. 2.2.2 DRV5032
      3. 2.2.3 TPS709
      4. 2.2.4 SN74HCS00
      5. 2.2.5 TPS22917
      6. 2.2.6 SN74AUP1G00
      7. 2.2.7 TLV9061
    3. 2.3 Design Considerations
      1. 2.3.1 Design Hardware Implementation
        1. 2.3.1.1 Hall-Effect Switches
          1. 2.3.1.1.1 U1 Wake-Up Sensor Configuration
          2. 2.3.1.1.2 U2 Stray-Field Sensor Configuration
          3. 2.3.1.1.3 U3 and U4 Tamper Sensor Configuration
          4. 2.3.1.1.4 Hall Switch Placement
            1. 2.3.1.1.4.1 Placement of U1 and U2 Sensors
              1. 2.3.1.1.4.1.1 U1 and U2 Magnetic Flux Density Estimation Results
            2. 2.3.1.1.4.2 Placement of U3 and U4 Hall Switches
              1. 2.3.1.1.4.2.1 U3 and U4 Magnetic Flux Density Estimation Results
          5. 2.3.1.1.5 Using Logic Gates to Combine Outputs from Hall-Effect Switches
        2. 2.3.1.2 Linear Hall-Effect Sensor Output
          1. 2.3.1.2.1 DRV5056 Power
          2. 2.3.1.2.2 DRV5056 Output Voltage
          3. 2.3.1.2.3 DRV5056 Placement
        3. 2.3.1.3 Power Supply
        4. 2.3.1.4 Transistor Circuit for Creating High-Voltage Enable Signal
      2. 2.3.2 Alternative Implementations
        1. 2.3.2.1 Replacing 20-Hz Tamper Switches With 5-Hz Tamper Switches
        2. 2.3.2.2 Using Shielding to Replace Tamper Switches and Stray Field Switch
        3. 2.3.2.3 Replacing Hall-Based Wake-Up Alert Function With a Mechanical Switch
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Installation and Demonstration Instructions
      2. 3.1.2 Test Points and LEDs
      3. 3.1.3 Configuration Options
        1. 3.1.3.1 Disabling Hall-Effect Switches
        2. 3.1.3.2 Configuring Hardware for Standalone Mode or Connection to External Systems
    2. 3.2 Test Setup
      1. 3.2.1 Output Voltage Accuracy Testing
      2. 3.2.2 Magnetic Tampering Testing
      3. 3.2.3 Current Consumption Testing
    3. 3.3 Test Results
      1. 3.3.1 Output Voltage Accuracy Pre-Calibration Results
      2. 3.3.2 Output Voltage Accuracy Post-Calibration Results
      3. 3.3.3 Magnetic Tampering Results
      4. 3.3.4 Current Consumption Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 サポート・リソース
    5. 4.5 Trademarks
2.3.1.1.5 Using Logic Gates to Combine Outputs from Hall-Effect Switches

If any of the tamper Hall sensors are enabled, logic gates are needed to combine the output of the multiple Hall-switches to produce one signal that provides information on whether the system should be in sleep mode. Figure 2-19 shows the schematic snippet of the logic gates.

GUID-20211214-SS0I-RHFC-49TH-PT0NVD94L5X3-low.gif Figure 2-19 Logic Circuit Schematic

If all the Hall-switches are enabled, there are three signals that are needed to properly provide information on whether the system should be in sleep mode:

  • Switch U2's output: The system should be placed in sleep mode if the outputs of both U1 and U2 are not asserted low. Since the GND of U2 is connected to the output of U1, the output of switch U2 is only asserted low when the output of switch U1 is asserted low.
  • Switch U3's output: If the output of U3 is asserted low, a strong magnetic field (the field can be positive or negative) is detected, so the system should be placed in sleep mode.
  • Switch U4's output: Similar to U3, if the output of U4 is asserted low, a strong magnetic field (the field can be positive or negative) is detected. This means the system should be placed in sleep mode.

The system should only be in active mode if the output of switch U2 is low, the output of U3 is high, and the output of U4 is high. In Figure 2-19, this is implemented by using the SN74HCS00 and SN74AUP1G00 to implement the following logic function: U 2 O U T ¯ U 3 O U T U 4 O U T , which is output at the LOGIC_OUT signal shown in Figure 2-19 . The complement of this signal is also available at the LOGIC signal shown in Figure 2-19. The SN74AUP1G00 is necessary since the active-high TPS22917 load switch is used. If the active-high TPS22917 load switch is replaced with the active-low TPS22916, the SN74AUP1G00 logic gate is not needed since the LOGIC signal can be connected directly to the TPS22916. Table 2-3 shows the system state truth table.

Table 2-3 System State Truth Table
U2 OUTPUT ASSERTION U3 OUTPUT ASSERTION U4 OUTPUT LOGIC_OUT STATE LOGIC STATE SYSTEM STATE CONDITIONS
Low Low Low Low High Sleep External magnetic field detected by both tamper switches. The trigger is also pressed or both the stray field and wake-up sensor are fooled by an external magnet in a configuration similar to Figure 2-12.
Low Low

High

 Low High

Sleep

 External magnetic field detected by tamper switch U3. Either the trigger is also pressed or both the stray field and wake-up sensor are fooled by an external magnet in a configuration similar to Figure 2-12.
Low High Low Low High Sleep External magnetic field detected by tamper switch U4. Either the trigger is also pressed or both the stray field and wake-up sensor are fooled by an external magnet in a configuration similar to Figure 2-12.
Low High High

High

Low

Active

Trigger is pressed without detecting external magnetic fields
High Low Low Low High Sleep External magnetic field detected by both tamper Hall switches. The trigger might not be pressed. If the trigger is pressed,both the wake-up and tamper sensors either detect a strong positive field or a strong negative field from an external source.
High Low High Low High Sleep External magnetic field detected by tamper switch U4. The trigger might not be pressed. If the trigger is pressed, both the wake-up and tamper sensors either detect a strong positive field or a strong negative field from an external source.
High High Low Low High Sleep External magnetic field detected by tamper switch U3. The trigger might not be pressed. If the trigger is pressed,

both the wake-up and tamper sensors either detect a strong positive field or a strong negative field from an external source.
High High High Low High Sleep External magnetic field not detected by tamper switches U3 and U4. The trigger might not be pressed. If the trigger is pressed,

both the wake-up and tamper sensors either detect a strong positive field or a strong negative field from an external source.

If using all the sensors is not desired, the logic gate can be configured to bypass the outputs from the Hall switches by configuring the R16, R17, and R18 3-pad footprints appropriately. By default, a 0-Ω resistor is placed at pads 2 and 3 of R16, R17, and R18, which takes the outputs from all the Hall switches and feeds it to the inputs of the logic gate. If U3 is disabled, move the 0-Ω resistor from pads 2 and 3 of R18 to pads 1 and 2, which causes the logic circuit to ignore the state of the U3 output. Similarly, if U4 is disabled, move the 0-Ω resistor from pads 2 and 3 of R17 to pads 1 and 2 so that the U3 output can be ignored by the logic circuit. If the stray field sensor is not needed, move the 0-Ω resistor from pads 2 and 3 of R16 to pads 1 and 2, which connects the output of U1 to logic circuit instead of the U2 stray-field sensor.