JAJU848 April   2022 TPSI3050 , TPSI3050-Q1 , TPSI3052 , TPSI3052-Q1

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
    3. 2.3 Design Considerations
      1. 2.3.1 Overcurrent Protection (OCP)
        1. 2.3.1.1 Immediate Overcurrent Protection
        2. 2.3.1.2 Adjustable Delay Overcurrent Protection
      2. 2.3.2 Overtemperature Protection (OTP)
        1. 2.3.2.1 TMP392
        2. 2.3.2.2 ISO7310
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Altium Project
      4. 4.1.4 Assembly Drawings
      5. 4.1.5 Gerber Files
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Author

2.3.1.1 Immediate Overcurrent Protection

When the system experiences a large overcurrent greater than 5 A, the overcurrent protection disconnects the load immediately. The sense resistor (R10) is selected to create a voltage drop of 300 mV at expected current limit. For this design a 5 A is the selected current limit threshold. When the current is higher than 5 A, OUT2 changes state from High-Z to Low-Z. Equation 3 shows the calculation for the sense resistor value.

Equation 3. R s e n s e   =   V T R I P _ F I X E D I F A U L T   =   300   m V 5   A   =   60   m Ω

The power rating of the shunt should be at least 30% higher than the peak power dissipation as a recommended design margin. The tolerance of the resistor should be 1% or less to allow for higher overcurrent protection accuracy. Equation 4 provides the calculation for the peak power dissipation across the sense resistor. For this design a resistor with a 3 W capability was selected for design margin.

Equation 4. P m a x   =   i 2   ×   R S E N S E   =   1 . 5   W

Figure 2-4 shows a detailed analysis of the charging and discharging paths. When the current load (ILOAD) through R10 is higher than 5 A, a voltage drop of 300 mV is created in R10. OUT2 is pulled to ground when the voltage drop is greater than 300 mV. When OUT2 is Low-Z, the input of the AND gate (SN74HCS09) is immediately pulled to ground, the output of the AND gate (EN) is asserted low and the load is disconnected. Discharge Path 2 in Figure 2-4 shows how C22 is discharged when OUT2 is pulled low. R16 is placed to limit the inrush current from C22 through OUT2. Since OUT1 and OUT2 are pulled low, C22 discharges below the negative switching threshold (VT-) of the AND gate in 180-us as the following equation shows. Note that the following equation only accounts for Discharging Path 2 for simplicity.

Equation 5. t d i s c h a r g e   =   -   R 16   ×   C 22   ×   ln V C 22 V S O U R C E   t d i s c h a r g e   =   -   1   k Ω   ×   220   n F   ×   ln 2 . 2   V 5   V   =   180 . 62   μ s

When the load is disconnected, the circuit attempts to reconnect the load automatically. When the voltage across the capacitor is charged above the positive switching threshold (VT+) of the AND gate, then EN is asserted high and the load connected. The AND gate (SN74HCS09) guarantees by design a minimum hysteresis of 0.4 V (VHYS). With this hysteresis value, the following equations shows that at least 38 ms will passed before the load is reconnected.

Equation 6. t c h a r g e   =   -   R 14 + R 17   ×   C 22   ×   ln V S O U R C E - ( V I N I T I A L + V H Y S )   V S O U R C E - V I N I T I A L   t c h a r g e   =   -   ( 560   k Ω   + 560   k Ω )     ×   220   n F   ×   ln 5   V   -   2 . 2   V   -   0 . 4   V 5   V   -   2 . 2   V   =   37 . 98   m s