JAJU850 May   2022 TPSI3050 , TPSI3050-Q1 , TPSI3052 , TPSI3052-Q1

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 System Design Theory
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
    3. 2.3 Design Considerations
      1. 2.3.1 TPSI3050-Q1
      2. 2.3.2 AMC23C10
      3. 2.3.3 SN74HCS72 and TMUX1219
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Altium Project
      4. 4.1.4 Assembly Drawings
        1. 4.1.4.1 Gerber Files
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Author

1.1 System Design Theory

The following section provides a complete summary of the reference design and the results. This reference design uses four main components (TPSI3050-Q1, AMC23C10, SN74HCS72, TMUX1219) in order to achieve zero-cross switching. Figure 1-2 shows the overall system behavior for the reference design.

  • AC supply is the ac source for the load.
  • OUT2 is the output of the isolated comparator (AMC23C10).
  • SEL is the output select signal for the multiplexer (TMUX1219).
  • EN is the enable signal for the isolated switch driver (TPSI3050-Q1).
  • ILOAD is the load current through the load.

When the AC supply is connected to the back to back MOSFETs, the antiparallel diodes D1 create a forward bias voltage drop that is used by the AMC23C10 to toggle OUT2. OUT2 toggles at every zero-cross of the AC supply. OUT2 signal is provided as a clock signal to the flip-flop SN74HCS72. SN74HCS72 is a D-type negative-edge-triggered flip-flop and will only change the output Q during the falling edge of the clock signal, in this case OUT2. SEL signals control the output of the multiplexer. While SEL is low, EN remains low maintaining the load disconnected. When SEL changes to high, the flip-flop awaits for the next falling edge and changes the output Q to high. The output of the multiplexer (EN) is toggled high and the load connected. When SEL signal is toggled low, the load is disconnected immediately.

This reference design was tested with a 110 VRMS, 60 Hz AC supply and a resistive load of 2 kΩ. The design switches ON at 12 V with a propagation delay (t2) of approximately 200 us from the zero voltage cross to when the load is connected. When SEL is toggled high, the load is not connected immediately and the system awaits for a zero-cross that produces a falling edge of OUT2. The await time from SEL to a load connection can be described by (t1+t2). The maximum await time is the case of a full cycle of the 60-Hz supply or t1 = 16.67 ms plus the propagation delay t2 = 200 us. This reference design features an immediate load disconnect. When SEL is toggled low, the load is immediately disconnected. Visit Section 3.3 for more information.

Figure 1-2 Zero-Cross Switching Operation