SBAA525A september   2021  – may 2023 AFE7900 , AFE7920 , AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Highlighted Products
    2. 1.2 Device Loopback Modes
      1. 1.2.1 ADC to DAC JESD Loopback
      2. 1.2.2 ADC to DAC Low Latency Loopback
  5. 2Tests and Results
    1. 2.1 Test Methodology
      1. 2.1.1 Hardware Setup
        1. 2.1.1.1 ADC to DAC JESD Loopback
        2. 2.1.1.2 ADC to DAC Low Latency Loopback
      2. 2.1.2 GUI Setup
        1. 2.1.2.1 ADC to DAC JESD Loopback
        2. 2.1.2.2 ADC to DAC Low Latency Loopback
      3. 2.1.3 Test Conditions
      4. 2.1.4 Test Results
        1. 2.1.4.1 ADC to DAC JESD Loopback
          1. 2.1.4.1.1 JESD 122.88 MSPS
          2. 2.1.4.1.2 JESD 184.32 MSPS
          3. 2.1.4.1.3 JESD 245.76 MSPS
          4. 2.1.4.1.4 JESD 368.64 MSPS
          5. 2.1.4.1.5 JESD 491.52 MSPS
        2. 2.1.4.2 ADC to DAC Low Latency Loopback
  6. 3Conclusion
  7. 4References
  8. 5Revision History

2.1.4.2 ADC to DAC Low Latency Loopback

In this mode, the device is tested with loopback without DDC and JESD interface achieving high analog signal bandwidth (approximately 1 GHz). Magnitude response does not reflect any attenuation in pass band which is more dependent to external matching network loop response. Group Delay measures approximately 49.48 ns demonstrating lowest latency feedback signal chain.

GUID-20210805-CA0I-LBRQ-MHL3-VFX2XBLXRPTN-low.pngFigure 2-14 Magnitude Response ADC to DAC Low Latency Loopback
GUID-20210805-CA0I-GSMG-HDJK-K6BR4RWHFKXT-low.pngFigure 2-15 Group Delay ADC to DAC Low Latency Loopback

There is a function named lowLatencyModeProgDelay(afeInst, chNo, progDelay) which can be used to vary the values of latency in this mode. Here, chNo is set to 0 for FBAB and 1 for FBCD. The value of progDelay can be varied from 0 to 23 where 0 corresponds to minimum latency. The loop latency increases as the value of progDelay is increased from 0 to 23.