SBAA525A september   2021  – may 2023 AFE7900 , AFE7920 , AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Highlighted Products
    2. 1.2 Device Loopback Modes
      1. 1.2.1 ADC to DAC JESD Loopback
      2. 1.2.2 ADC to DAC Low Latency Loopback
  5. 2Tests and Results
    1. 2.1 Test Methodology
      1. 2.1.1 Hardware Setup
        1. 2.1.1.1 ADC to DAC JESD Loopback
        2. 2.1.1.2 ADC to DAC Low Latency Loopback
      2. 2.1.2 GUI Setup
        1. 2.1.2.1 ADC to DAC JESD Loopback
        2. 2.1.2.2 ADC to DAC Low Latency Loopback
      3. 2.1.3 Test Conditions
      4. 2.1.4 Test Results
        1. 2.1.4.1 ADC to DAC JESD Loopback
          1. 2.1.4.1.1 JESD 122.88 MSPS
          2. 2.1.4.1.2 JESD 184.32 MSPS
          3. 2.1.4.1.3 JESD 245.76 MSPS
          4. 2.1.4.1.4 JESD 368.64 MSPS
          5. 2.1.4.1.5 JESD 491.52 MSPS
        2. 2.1.4.2 ADC to DAC Low Latency Loopback
  6. 3Conclusion
  7. 4References
  8. 5Revision History

2.1.1.1 ADC to DAC JESD Loopback

Vector Network Analyzer port 1 is connected to RXD channel of device, TXD channel is reconnected to port 2 of Vector Network Analyzer to capture group delay and loop gain. Vector Network Analyzer internally sweeps across bandwidth set relative to SERDES data rates.

GUID-20210810-SS0I-NLHK-P29W-BQWLNB40LSRS-low.png Figure 2-1 HW Block Diagram – JESD Loopback