SBAA525A september   2021  – may 2023 AFE7900 , AFE7920 , AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Highlighted Products
    2. 1.2 Device Loopback Modes
      1. 1.2.1 ADC to DAC JESD Loopback
      2. 1.2.2 ADC to DAC Low Latency Loopback
  5. 2Tests and Results
    1. 2.1 Test Methodology
      1. 2.1.1 Hardware Setup
        1. 2.1.1.1 ADC to DAC JESD Loopback
        2. 2.1.1.2 ADC to DAC Low Latency Loopback
      2. 2.1.2 GUI Setup
        1. 2.1.2.1 ADC to DAC JESD Loopback
        2. 2.1.2.2 ADC to DAC Low Latency Loopback
      3. 2.1.3 Test Conditions
      4. 2.1.4 Test Results
        1. 2.1.4.1 ADC to DAC JESD Loopback
          1. 2.1.4.1.1 JESD 122.88 MSPS
          2. 2.1.4.1.2 JESD 184.32 MSPS
          3. 2.1.4.1.3 JESD 245.76 MSPS
          4. 2.1.4.1.4 JESD 368.64 MSPS
          5. 2.1.4.1.5 JESD 491.52 MSPS
        2. 2.1.4.2 ADC to DAC Low Latency Loopback
  6. 3Conclusion
  7. 4References
  8. 5Revision History

1.2.1 ADC to DAC JESD Loopback

AFE79xx supports internal digital JESD loopback as shown in Figure 1-1 without the need of external STX and SRX lane connection. The internal 20-bit digital stream loopback has been tested by driving RXD using vector network analyzer for gain and group delay parameter plot having 12-GSPS DAC output and multiple JESD data rate from 122.88 MSPS to 491.52 MSPS. The bandwidth is measured across signal tone of 3.4 GHz to demonstrate loopback function for 5G n78 band. The device can also be configured for different frequency bands by tuning external matching circuit accordingly.

GUID-20210805-CA0I-QS4S-HL99-BN0RCLXPD2V7-low.gif Figure 1-1 ADC to DAC JESD Loopback

Data sheet Switching Characteristics highlights expected latency across different SERDES rates as function of internal clock cycle as shown in Table 1-1.

Overall delay is total latency introduced in signal path due to matching element, RX input to JESD output latency, JESD to TX output latency and internal delay of VNA.

If we take 122.88 MSPS as an example, total internal delay of AFE79xx is 189 clock cycles at 122.88 MHz which approximates to 1.53 us. With external matching elements thus we can achieve sub 2-us group latency response.

Table 1-1 Switching Characteristics at TA= 25°C, full temperature range is TA, MIN = -40°C to TJ, MAX = +110°C; TX Input Rate = 737.28 MSPS, fDAC= 8847.36 MSPS; fADC = 2949.12 MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation = 0 dB, SerDes rate = 24.33 Gbps; unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TX CHANNEL LATENCY
SerDes Receiver Analog Delay Full Rate 2.8 ns
JESD to TX Ouput Latency LMFSHd = 2-8-8-1, 368.64 MSPS input rate, 24x Interpolation, Serdes rate = 16.22 Gbps (JESD204C) 152 Interface Clock Cycles
LMFSHd = 8-16-4-1, 491.52 MSPS input rate, 24x Interpolation, Serdes rate = 16.22 Gbps (JESD204C) 176
LMFSHd = 4-16-8-1, 245.76 MSPS input rate, 48x Interpolation, Serdes rate = 16.22 Gbps (JESD204C) 124
LMFSHd = 2-16-16-1, 122.88 MSPS input rate, 96x Interpolation, Serdes rate = 16.22 Gbps (JESD204C) 97
RX CHANNEL LATENCY
SerDes Transmitter Analog Delay 3.6 ns
RX Input to JESD Ouput Latency LMFS = 2-8-8-1, 368.64 MSPS input rate, 8x Decimation, Serdes rate = 16.22 Gbps (JESD204C) 118 Interface Clock Cycles
LMFS = 2-16-16-1, 122.88 MSPS input rate, 24x Decimation, Serdes rate = 16.22 Gbps (JESD204C) 92
LMFS = 4-16-8-1, 245.76 MSPS input rate, 12x Decimation, Serdes rate = 16.22 Gbps (JESD204C) 108
LMFS = 4-8-4-1, 491.52 MSPS input rate, 6x Decimation, Serdes rate = 16.22 Gbps (JESD204C) 153
FB CHANNEL LATENCY
SerDes Transmitter Analog Delay 3.6 ns
FB Input to JESD Ouput Latency LMFS = 1-2-8-1, 368.64 MSPS, 8x Decimation 151 Interface Clock Cycles
LMFS = 2-4-4-1, 491.52 MSPS, 6x Decimation 177