This user's guide explains the methods to align multiple JESD204 receiver lanes in AFE79xx using Receive Buffer Delay (RBD). In practice, the JESD204 receiver requires buffering of various delays in the received lanes in order to ensure deterministic data throughout the data bus. A key feature in AFE79xx can optimize the buffer pointer through internal lane-to-lane skew and arrival of lane time stamps with respect to the JESD204 clock. The AFE79xx JESD204 receiver block has unique features to read the skew and arrival of lanes with respect to Local Multi Frame Clock (LMFC)/ Local Extended Multiblock Clock (LEMC) clock to help find the right RBD for the system.
The user's guide is structured as follows:
All trademarks are the property of their respective owners.
The AFE79xx is a family of high-performance, wide bandwidth multi-channel transceivers, which includes four RF sampling transmitter chains. The transmitters support up to 1200-MHz wide bandwidth, which is designed for multi-band 4G and 5G base stations. Such high bandwidths demand up to 198 Gbps serial data transmission. For this reason, a maximum of 8 lanes are used to receive high bandwidth input for the DAC.
Each DAC takes a 16-bit I input and 16-bit Q input stream. For high bandwidth cases, the complex I and Q data reception can be spread among 4 input lanes. Figure 1-1 shows an example where the DAC JESD is configured with an LMFS(1) of 4222. Even with small form factor flip chip ball grid array (BGA) and symmetrical Serdes input and output ball placement, the PCB routing design cannot perfectly match all the SerDes I/O lanes. This causes a skew among lanes, which causes misalignment between the lanes. At the FPGA, data I0, I1, Q0 and Q1 are time aligned. As it traverses through the lanes and arrives at the AFE, the time alignment has been lost. If this is input to the DAC as it is, the spectrum observed at the DAC would be a lot different to what was expected. This example highlights the need to de-skew the receiver lanes in AFE. The role of RBD in JESD layer is exactly this.
Even in cases where a single lane carries data of each DAC, as in DAC JESD LMFS = 24410, it is critical to align the data on multiple lanes. Deterministic latency across power-up cycles necessitates this alignment across lanes. The path latency from FPGA to DAC is a critical metric and RBD helps with maintaining this deterministic latency across transmitter channels and across power-up cycles.
Standard JESD204 Definition for JESD204 Lane and Data Packing Configuration.
L = Number of Lanes
M = Number of Converters
F = Number of Octets per Frame
S = Number of Samples per Frame
This section provides a very brief review of JESD204C protocol, so as to understand terminologies related to setting the optimal RBD.
JESD204C implements 64b/66b encoding. To each set of eight octets (64 bits), two pilot bits called sync header are inserted. The 2 bits in sync header are invert of each other, which means the sync header can only be 10 or 01. With this unique property of sync header, the JESD receiver identifies and locks on to the 66-bit boundary. These 66 bits are termed as blocks.
The blocks are then built into a multiblock, that consists of 32 blocks, as shown in Figure 2-1(1). The sync header SH0 to SH31 follow a pattern as described in the protocol, which helps the JESD receiver lock onto the multiblock boundary.
Further, ‘E’ number of multiblocks are combined into a extended multiblock. The parameter ‘E’ is configurable in Latte -
sysParams.jesdRxK
Typically, for 16-bit data packing (that is, typical F = 1, 2, 4, or 8 cases), E is set to 1. For 12-bit data packing (that is, F = 3 or F = 6 cases) patterns E is set to 3, so that each extended multiblock contains an integer number of samples and integer number of frames. The information stored in sync header, specifically SH22, is used to identify the end of an extended multiblock.
The JESD receiver uses a LEMC to correct for the skew between lanes. The LEMC period is equal to the extended multi-block period. For example,
To ensure that the processing clock LEMC, between the JESD204 transmitter and JESD204 receiver, are aligned at start-up of the system without drift or wander, a global system reference clock (SYSREF) provides the clock synchronization and alignment. The SYSREF frequency is an integer factor of LEMC frequency. The SYSREF is distributed throughout the JESD204 system in a time aligned, fixed delay manner throughout various temperature cycle and system restart cycle. Since SYSREF is essentially deterministic, the data transfer through the JESD204 link will also be deterministic.
To compensate for the lane-to-lane skew, the JESD204C receiver has an internal buffer to first absorb the skews amongst all the lanes, and then re-align the lanes at the output of the buffer upon the release of the buffer. This essentially created a zero-skew environment for data processing at the output the JESD204C receiver. This is highlighted in Figure 2-2(1).
The buffer and the release of the buffer is controlled by RBD, or receive buffer delay. Finding the optimal RBD value in a system that will work across various temperature and restart cycle is essential in the overall system stability.
In the JESD204C transmitter, the Start of Extended Multi Block (SoEMB as shown in Figure 2-2) shall be initiated simultaneously across all lanes at a well-defined moment in time. The ‘well-defined moment in time’ is a deterministic period of time from the LEMC edge.
In the JESD204C receiver, to align data across lanes, a buffer exists to hold all lane data for release simultaneously at a well-defined moment in time. The ‘well-defined moment in time’ for RX buffer release is a programmable number of steps after an active LEMC edge. This programmable number of steps is referred to as the Receive Buffer Delay (RBD).
Parts of figures were based on JEDEC JESD204C standard, Figure 5 and Figure 50. Copyright JEDEC. Modifications have not been approved by and do not reflect the views of JEDEC.
Parts of figures were based on JEDEC JESD204C standard, Figure 5 and Figure 50. Copyright JEDEC. Modifications have not been approved by and do not reflect the views of JEDEC.
This section describes the procedure to be followed for setting the optimal RBD. Figure 2-3(1) depicts the available features in AFE79xx to readout various latencies, including lane arrival delay and skew among lanes.
Internal to AFE79xx, there exists a LEMC counter which operates on a clock with frequency of LaneRate/33. The counter is periodic with the LEMC, whose frequency is LaneRate/(66*32*E). The LEMC counter counts 64 times faster than the internal LEMC frequency, and therefore, the LEMC counter will count from 0 to 64*E-1, as shown in Figure 2-3. There is also an option to add an offset to this counter by use of link0/1_init_f_counter. In Latte, this can be done by setting the system parameter jesdRxInitLmfcCounter. For example, as per Figure 2-3,
sysParams.jesdRxInitLmfcCounter = 5
can be added to the Latte bringup. For more details, see Section 5.2.
Lane arrival information can be read back from lane0/1/2/3_f_counter_any_lane_ready. lane0/1/2/3_f_counter_any_lane_ready is the value of LEMC counter when the start of EMB arrives at the corresponding lane. Figure 2-3 shows such an example for JESD lane 0 and JESD lane 3. The start of EMB arrives at JESD lane 0 when the LEMC counter is 3, this information can be read back from lane0_f_counter_any_lane_ready. Similarly, lane3_f_counter_any_lane_ready would read as 6.
The instant last lane arrives is critical information for setting the RBD. This information can be read back from lane0/1/2/3_f_counter_all_lane_ready. lane0/1/2/3_f_counter_all_lane_ready would be equal to the lane_f_counter_any_lane_ready of slowest lane. In the case shown in Figure 2-3, the last lane to arrive is JESD lane 3. So, lane0/1/2/3_f_counter_all_lane_ready would read the same as lane3_f_counter_any_lane_ready, which is 6.
lane0/1/2/3_skew equals the difference between the LEMC counter values for earliest arrival lane and latest arrival lane. In Figure 2-3, it is difference between lane3_f_counter_any_lane_ready and lane0_f_counter_any_lane_ready. So lane0/1/2/3_skew would read 3.
With such visibility to lane arrival information in AFE79xx, it becomes easy to estimate the optimal RBD value. The recommended calculation for RBD is as follows.
The range of valid values the RBD can take is described by below condition
and
Default value of buffer depth is 32. Buffer depth is configurable – value of (link0/1_buffer_depth + 1) determines the buffer depth. The register link0_buffer_depth can take values from 0 to 31, meaning buffer depth can vary from 1 to 32.
link0_rbd_m1 is written to with value of the value of RBD. Register map and procedure to be followed in system bringup is described in detail in Section 4. Below examples describe the basic RBD calculation.
From the latest arrival lane, a margin of 4 is accounted for to include temperature and process variations. Once the margin is added, modulus operation is performed with 64*E. This is because the LEMC counter counts from 0 to a maximum of 64*E-1. The buffer releases the aligned data on all lanes once the LEMC counter reaches the RBD value. In the example shown in Figure 2-3, the RBD is set to 10, which is 4 LEMC counter value ahead of latest arrival lane. Few more examples are shown below. The value of skew is assumed to be 3 in the examples.
Example 1
Example 2
Example 3
Parts of figures were based on JEDEC JESD204C standard, Figure 5 and Figure 50. Copyright JEDEC. Modifications have not been approved by and do not reflect the views of JEDEC.