SBAA600 October   2024 TAA5212 , TAC5111 , TAC5112 , TAC5211 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Voice Activity Detection
    1. 2.1 VAD Configurations
      1. 2.1.1 User, Auto, Intermediate
      2. 2.1.2 VAD With ADC Recording
      3. 2.1.3 VAD Monitoring Channel
      4. 2.1.4 VAD Interrupt Pin
      5. 2.1.5 MICBIAS Enable During PDM Monitoring
      6. 2.1.6 VAD Clock Configurabilty
    2. 2.2 VAD Parameters
      1. 2.2.1 Initial Learning Period
      2. 2.2.2 Hold Over Counter
      3. 2.2.3 Wakeup Wait
      4. 2.2.4 Threshold
  6. 3VAD Performance Results
  7. 4Examples
  8. 5Summary
  9. 6References

2.1.2 VAD With ADC Recording

This parameter decides if voice activity needs to be detected when ADC is recording is ongoing or not. If this bit is enabled, then the VAD algorithm continues running when ADC recording is in progress to detect any voice activity. Running the VAD while the ADC is recording is considered High Power Mode.

As Table 2-4 shows, VAD ON during recording selection is done using the LPAD_PD_DET_EN bit of LPAD_CFG1[1] register (page = 0x01, address = 0x1E).

Table 2-4 VAD ON During Recording Selection Using VAD_CFG2 Register
Bit Field Type Reset Description
1 VAD_PD_DET_EN R/W 1b Enable ASI output data during VAD activity.
0d = VAD processing is not enabled during ADC recording
1d = VAD processing is enabled during ADC recording and VAD interrupts are generated as configured