SBAS426H August   2008  – March 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Timing Requirements
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  ADC Input and Multiplexer
      2. 9.3.2  Low-Noise PGA
        1. 9.3.2.1 PGA Common-Mode Voltage Requirements
        2. 9.3.2.2 PGA Common-Mode Voltage Calculation Example
        3. 9.3.2.3 Analog Input Impedance
      3. 9.3.3  Clock Source
      4. 9.3.4  Modulator
      5. 9.3.5  Digital Filter
      6. 9.3.6  Voltage Reference Input
      7. 9.3.7  Internal Voltage Reference
      8. 9.3.8  Excitation Current Sources
      9. 9.3.9  Sensor Detection
      10. 9.3.10 Bias Voltage Generation
      11. 9.3.11 General-Purpose Digital I/O
      12. 9.3.12 System Monitor
        1. 9.3.12.1 Power-Supply Monitor
        2. 9.3.12.2 External Voltage Reference Monitor
        3. 9.3.12.3 Ambient Temperature Monitor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Up
      2. 9.4.2 Reset
      3. 9.4.3 Power-Down Mode
      4. 9.4.4 Conversion Control
        1. 9.4.4.1 Settling Time for Channel Multiplexing
        2. 9.4.4.2 Channel Cycling and Overload Recovery
        3. 9.4.4.3 Single-Cycle Settling
        4. 9.4.4.4 Digital Filter Reset Operation
      5. 9.4.5 Calibration
        1. 9.4.5.1 Offset Calibration Register: OFC[2:0]
        2. 9.4.5.2 Full-Scale Calibration Register: FSC[2:0]
        3. 9.4.5.3 Calibration Commands
          1. 9.4.5.3.1 System Offset and Self Offset Calibration
          2. 9.4.5.3.2 System Gain Calibration
        4. 9.4.5.4 Calibration Timing
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Ready (DRDY)
        5. 9.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 9.5.1.6 SPI Reset
        7. 9.5.1.7 SPI Communication During Power-Down Mode
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  WAKEUP (0000 000x)
        2. 9.5.3.2  SLEEP (0000 001x)
        3. 9.5.3.3  SYNC (0000 010x)
        4. 9.5.3.4  RESET (0000 011X)
        5. 9.5.3.5  RDATA (0001 001x)
        6. 9.5.3.6  RDATAC (0001 010x)
        7. 9.5.3.7  SDATAC (0001 011x)
        8. 9.5.3.8  RREG (0010 rrrr, 0000 nnnn)
        9. 9.5.3.9  WREG (0100 rrrr, 0000 nnnn)
        10. 9.5.3.10 SYSOCAL (0110 0000)
        11. 9.5.3.11 SYSGCAL (0110 0001)
        12. 9.5.3.12 SELFOCAL (0110 0010)
        13. 9.5.3.13 NOP (1111 1111)
        14. 9.5.3.14 Restricted Command (1111 0001)
    6. 9.6 Register Maps
      1. 9.6.1 ADS1246 Register Map
      2. 9.6.2 ADS1246 Detailed Register Definitions
        1. 9.6.2.1 BCS—Burn-out Current Source Register (offset = 00h) [reset = 01h]
        2. 9.6.2.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.2.3 MUX—Multiplexer Control Register (offset = 02h) [reset = x0h]
        4. 9.6.2.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.2.5 OFC—Offset Calibration Coefficient Registers (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.2.6 FSC—Full-Scale Calibration Coefficient Registers (offset = 07h, 08h, 09h) [reset = PGA dependent]
        7. 9.6.2.7 ID—ID Register (offset = 0Ah) [reset = x0h]
      3. 9.6.3 ADS1247 and ADS1248 Register Map
      4. 9.6.4 ADS1247 and ADS1248 Detailed Register Definitions
        1. 9.6.4.1  MUX0—Multiplexer Control Register 0 (offset = 00h) [reset = 01h]
        2. 9.6.4.2  VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.4.3  MUX1—Multiplexer Control Register 1 (offset = 02h) [reset = x0h]
        4. 9.6.4.4  SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.4.5  OFC—Offset Calibration Coefficient Register (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.4.6  FSC—Full-Scale Calibration Coefficient Register (offset = 07h, 08h, 09h) [reset = PGA dependent]
        7. 9.6.4.7  IDAC0—IDAC Control Register 0 (offset = 0Ah) [reset = x0h]
        8. 9.6.4.8  IDAC1—IDAC Control Register 1 (offset = 0Bh) [reset = FFh]
        9. 9.6.4.9  GPIOCFG—GPIO Configuration Register (offset = 0Ch) [reset = 00h]
        10. 9.6.4.10 GPIODIR—GPIO Direction Register (offset = 0Dh) [reset = 00h]
        11. 9.6.4.11 GPIODAT—GPIO Data Register (offset = 0Eh) [reset = 00h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
      8. 10.1.8 Channel Multiplexing Example
      9. 10.1.9 Power-Down Mode Example
    2. 10.2 Typical Applications
      1. 10.2.1 Ratiometric 3-Wire RTD Measurement System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Topology
          2. 10.2.1.2.2 RTD Selection
          3. 10.2.1.2.3 Excitation Current
          4. 10.2.1.2.4 Reference Resistor RREF
          5. 10.2.1.2.5 PGA Setting
          6. 10.2.1.2.6 Common-Mode Input Range
          7. 10.2.1.2.7 Input and Reference Low-Pass Filters
          8. 10.2.1.2.8 Register Settings
        3. 10.2.1.3 Application Curves
      2. 10.2.2 K-Type Thermocouple Measurement (-200°C to +1250°C) with Cold-Junction Compensation
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Biasing Resistors
          2. 10.2.2.2.2 Input Filtering
          3. 10.2.2.2.3 PGA Setting
          4. 10.2.2.2.4 Cold-Junction Measurement
          5. 10.2.2.2.5 Calculated Resolution
          6. 10.2.2.2.6 Register Settings
    3. 10.3 Do's and Don'ts
  11. 11Power-Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Power-supply voltage AVDD to AVSS –0.3 5.5 V
AVSS to DGND –2.8 0.3
DVDD to DGND –0.3 5.5
Analog input voltage AINx, REFPx, REFNx, VREFOUT, VREFCOM, IEXC1, IEXC2 AVSS – 0.3 AVDD + 0.3 V
Digital input voltage SCLK, DIN, DOUT/DRDY, DRDY, CS, START, RESET, CLK DGND – 0.3 DVDD + 0.3 V
Input current Continuous, any pin except power supply pins –10 10 mA
Momentary, any pin except power supply pins –100 100
Temperature Junction, TJ 150 °C
Storage, Tstg –60 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
Analog power supply AVDD to AVSS 2.7 5.25 V
AVSS to DGND –2.65 0.1
AVDD to DGND 2.25 5.25
Digital power supply DVDD to DGND 2.7 5.25 V
ANALOG INPUTS(2)
VIN Differential input voltage V(AINP) – V(AINN)(1) –VREF / Gain VREF / Gain V
VCM Common-mode input voltage (V(AINP) + V(AINN)) / 2 See Equation 3 V
VOLTAGE REFERENCE INPUTS(3)
VREF Differential reference input voltage V(REFPx) – V(REFNx) 0.5 (AVDD – AVSS) – 1 V
V(REFNx) Absolute negative reference voltage AVSS – 0.1 V(REFPx) – 0.5 V
V(REFPx) Absolute positive reference voltage V(REFNx) + 0.5 AVDD + 0.1 V
EXTERNAL CLOCK INPUT(4)
fCLK External clock frequency 1 4.5 MHz
External clock duty cycle 25% 75%
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIO)
GPIO input voltage AVSS AVDD V
DIGITAL INPUTS
Digital input voltage DGND DVDD V
TEMPERATURE RANGE
TA Operating ambient temperature –40 125 °C
Specified ambient temperature –40 105 °C
(1) For VREF > 2.7 V, the differential input voltage must not exceed 2.7 V / Gain.
(2) AINP and AINN denote the positive and negative inputs of the PGA.
(3) REFPx and REFNx denote the differential reference input pair (ADS1246, ADS1247), or one of the two available differential reference input pairs (ADS1248).
(4) External clock only required if the internal oscillator is not used.

7.4 Thermal Information

THERMAL METRIC(1) ADS1246 ADS1247 ADS1248 UNIT
PW (TSSOP) PW (TSSOP) PW (TSSOP)
16 PINS 20 PINS 28 PINS
RθJA Junction-to-ambient thermal resistance 95.2 87.6 54.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 28.8 21.2 11.3 °C/W
RθJB Junction-to-board thermal resistance 41.1 39.9 13 °C/W
ψJT Junction-to-top characterization parameter 1.5 0.8 0.5 °C/W
ψJB Junction-to-board characterization parameter 40.4 39.2 12.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

Minimum and maximum specifications apply from TA = –40°C to 105°C. Typical specifications are at TA = 25°C.
All specifications are at AVDD = 5 V, DVDD = 3.3 V, AVSS = 0 V, external VREF = 2.048 V, and fCLK = 4.096 MHz (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Differential input current 100 pA
Absolute input current See Table 8
PGA
PGA gain settings 1, 2, 4, 8, 16, 32, 64, 128 V/V
SYSTEM PERFORMANCE
Resolution 24 Bits
DR Data rate 5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000 SPS
ADC conversion time Single-cycle settling
INL Integral nonlinearity Differential input, end point fit,
Gain = 1, VCM = 2.5 V		 6 15 ppm
VIO Offset voltage (input referred) After calibration(3) –15 15 μV
Offset drift See Figure 9 to Figure 12
Gain error TA = 25°C, all Gains,
DR = 40 SPS, 80 SPS, or 160 SPS		 –0.02% ±0.005% 0.02%
Gain drift See Figure 17 to Figure 20
Noise See Table 1 to Table 4
NMRR Normal-mode rejection See Table 10
CMRR Common-mode rejection At DC, Gain = 1 80 90 dB
At DC, Gain = 32 90 125
PSRR Power-supply rejection AVDD / DVDD at DC,
Gain = 32, DR = 80 SPS		 100 135 dB
VOLTAGE REFERENCE INPUTS
Reference input current 30 nA
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage 2.038 2.048 2.058 V
Reference drift(2) TA = 25°C to 105°C 2 10 ppm/°C
TA = –40°C to 105°C 6 15 ppm/°C
Output current(1) –10 10 mA
Load regulation 50 μV/mA
Start-up time See Table 11
INTERNAL OSCILLATOR
Internal oscillator frequency 3.89 4.096 4.3 MHz
EXCITATION CURRENT SOURCES (IDACs)
Output current settings 50, 100, 250, 500, 750, 1000, 1500 μA
Compliance voltage All currents See Figure 41 and Figure 42
Absolute error All currents, each IDAC –6% ±1% 6%
Absolute mismatch All currents, between IDACs ±0.15%
Temperature drift Each IDAC 100 ppm/°C
Temperature drift matching Between IDACs 10 ppm/°C
BURN-OUT CURRENT SOURCES
Burn-out current source settings 0.5, 2, 10 μA
BIAS VOLTAGE
Bias voltage (AVDD + AVSS) / 2 V
Bias voltage output impedance 400 Ω
TEMPERATURE SENSOR
Output voltage TA = 25°C 118 mV
Temperature coefficient 405 μV/°C
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIO)
VIL Low-level input voltage AVSS 0.3 × AVDD V
VIH High-level input voltage 0.7 × AVDD AVDD V
VOL Low-level output voltage IOL = 1 mA 0.2 × AVDD V
VOH High-level output voltage IOH = 1 mA 0.8 × AVDD V
DIGITAL INPUTS/OUTPUTS (other than GPIO)
VIL Low-level input voltage DGND 0.3 × DVDD V
VIH High-level input voltage 0.7 × DVDD DVDD V
VOL Low-level output voltage IOL = 1 mA DGND 0.2 × DVDD V
VOH High-level output voltage IOH = 1 mA 0.8 × DVDD V
Input leakage DGND < VIN < DVDD –10 10 μA
POWER SUPPLY
IAVDD Analog supply current Power-down mode 0.1 µA
Converting, AVDD = 3.3 V,
DR = 20 SPS, external reference		 200
Converting, AVDD = 5 V,
DR = 20 SPS, external reference		 225
Additional current with internal reference enabled 180
IDVDD Digital supply current Power-down mode 0.2 μA
Normal operation, DVDD = 3.3 V,
DR = 20 SPS, internal oscillator		 210
Normal operation, DVDD = 5 V,
DR = 20 SPS, internal oscillator		 230
PD Power dissipation AVDD = DVDD = 5 V,
DR = 20 SPS, internal oscillator, external reference		 2.3 mW
AVDD = DVDD = 3.3 V,
DR = 20 SPS, internal oscillator, external reference		 1.4
(1) Do not exceed this loading on the internal voltage reference.
(2) Specified by the combination of design and final production test.
(3) Offset calibration on the order of noise.

7.5 Timing Requirements

At TA = –40°C to 105°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
SERIAL INTERFACE (SEE Figure 1 AND Figure 2)
tCSSC Delay time, First SCLK rising edge after CS falling edge 10 ns
tSCCS Delay time, CS rising edge after final SCLK falling edge 7 tCLK(1)
tCSPW Pulse duration, CS high 5 tCLK
tSCLK SCLK period 488 ns
64 Conversions
tSPWH Pulse duration, SCLK high 0.25 0.75 tSCLK
tSPWL Pulse duration, SCLK low 0.25 0.75 tSCLK
tDIST Setup time, DIN valid before SCLK falling edge 5 ns
tDIHD Hold time, DIN valid after SCLK falling edge 5 ns
tSTD Setup time, SCLK low before DRDY rising edge 5 tCLK
tDTS Delay time, SCLK rising edge after DRDY falling edge 1 tCLK
MINIMUM START TIME PULSE DURATION (SEE Figure 3)
tSTART Pulse duration, START high 3 tCLK
RESET PULSE DURATION, SERIAL INTERFACE COMMUNICATION AFTER RESET (SEE Figure 4)
tRESET Pulse duration, RESET low 4 tCLK
tRHSC Delay time, SCLK rising edge (start of serial interface communication) after RESET rising edge 0.6(2) ms
(1) tCLK = 1 / fCLK. The default clock frequency fCLK = 4.096 MHz.
(2) Applicable only when fCLK = 4.096 MHz, scales proportionally with fCLK frequency.

7.6 Switching Characteristics

At TA = –40°C to 105°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted; see Figure 1 and Figure 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDOPD Propagation delay time,
SCLK rising edge to valid new DOUT		 DVDD ≤ 3.6 V 50 ns
DVDD > 3.6 V 180
tDOHD DOUT hold time 0 ns
tCSDO Propagation delay time,
CS rising edge to DOUT high impedance		 10 ns
tPWH Pulse duration, DRDY high 3 tCLK
ADS1246 ADS1247 ADS1248 timing_ser_int_sbas426.gif Figure 1. Serial Interface Timing, DRDY MODE Bit = 0
ADS1246 ADS1247 ADS1248 timing_rdatac_sbas426.gif
1. This timing diagram is applicable only when the CS pin is low. SCLK does not need to be low during tSTD when CS is high.
2. SCLK must only be sent in multiples of eight during partial retrieval of output data.
Figure 2. Serial Interface Timing to Allow Conversion Result Loading1
ADS1246 ADS1247 ADS1248 timing_start_bas426.gif Figure 3. Minimum Start Pulse Duration
ADS1246 ADS1247 ADS1248 timing_reset_bas426.gif Figure 4. Reset Pulse Duration and Serial Interface Communication After Reset

7.7 Typical Characteristics

At TA = 25°C, AVDD = 5 V, AVSS = 0 V, and external VREF = 2.5 V (unless otherwise noted)
ADS1246 ADS1247 ADS1248 tc_inl-input_1_20_bas426.gif
Figure 5. Integral Nonlinearity vs Input Signal
ADS1246 ADS1247 ADS1248 tc_inl-input_128_20_bas426.gif
Figure 7. Integral Nonlinearity vs Input Signal
ADS1246 ADS1247 ADS1248 tc_oset-tmp_dr20_5v_bas426.gif
Figure 9. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_oset-tmp_dr640_5v_bas426.gif
Figure 11. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_odrift-tmp_dr20_33v_bas426.gif
Figure 13. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_oset-tmp_dr640_33v_bas426.gif
Figure 15. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr20_5v_bas426.gif
Figure 17. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr640_5v_bas426.gif
Figure 19. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr20_33v_bas426.gif
Figure 21. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr640_33v_bas426.gif
Figure 23. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_histo_pga1_5v_bas426.gif
Figure 25. Noise Histogram Plot
ADS1246 ADS1247 ADS1248 tc_histo_pga1_33v_bas426.gif
Figure 27. Noise Histogram Plot
ADS1246 ADS1247 ADS1248 tc_noise-input_5v_bas426.gif
Figure 29. RMS Noise vs Input Signal
ADS1246 ADS1247 ADS1248 tc_cmrr-tmp_bas426.gif
Figure 31. CMRR vs Temperature
ADS1246 ADS1247 ADS1248 tc_histo_vref_acc_bas426.gif
Figure 33. Internal VREF Initial Accuracy Histogram
ADS1246 ADS1247 ADS1248 tc_Vref_1000hrdrift_bas453.png
Figure 35. Internal Reference Long-Term Drift
ADS1246 ADS1247 ADS1248 tc_histo_idac_acc_bas426.gif
Figure 37. IDAC Initial Accuracy Histogram
ADS1246 ADS1247 ADS1248 tc_idac_line_reg_bas426.gif
Figure 39. IDAC Line Regulation
ADS1246 ADS1247 ADS1248 tc_idac_compliance2_bas453.png
Figure 41. IDAC Voltage Compliance
ADS1246 ADS1247 ADS1248 tc_analog-data_rate_bas426.gif
Figure 43. Analog Supply Current vs Data Rate
ADS1246 ADS1247 ADS1248 tc_analog-tmp_bas426.gif
Figure 45. Analog Supply Current vs Temperature
ADS1246 ADS1247 ADS1248 tc_ana_cur-tmp_bas426.gif
Figure 47. Analog Supply Current vs Temperature
ADS1246 ADS1247 ADS1248 tc_inl-input_32_20_bas426.gif
Figure 6. Integral Nonlinearity vs Input Signal
ADS1246 ADS1247 ADS1248 tc_inl-input_1_2k_bas426.gif
Figure 8. Integral Nonlinearity vs Input Signal
ADS1246 ADS1247 ADS1248 tc_oset-tmp_dr160_5v_bas426.gif
Figure 10. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_oset-tmp_dr2k_5v_bas426.gif
Figure 12. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_odrift-tmp_dr160_33v_bas426.gif
Figure 14. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_oset-tmp_dr2k_bas426.gif
Figure 16. Offset vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr160_5v_bas426.gif
Figure 18. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr2k_5v_bas426.gif
Figure 20. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr160_33v_bas426.gif
Figure 22. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_g-tmp_dr2k_33v_bas426.gif
Figure 24. Gain Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_histo_pga32_5v_bas426.gif
Figure 26. Noise Histogram Plot
ADS1246 ADS1247 ADS1248 tc_histo_pga32_33v_bas426.gif
Figure 28. Noise Histogram Plot
ADS1246 ADS1247 ADS1248 tc_noise-input_3v_bas426.gif
Figure 30. RMS Noise vs Input Signal
ADS1246 ADS1247 ADS1248 tc_psr-g_bas426.gif
Figure 32. Power-Supply Rejection vs Gain
ADS1246 ADS1247 ADS1248 tc_vref-tmp_bas426.gif
Figure 34. Internal VREF vs Temperature
ADS1246 ADS1247 ADS1248 tc_data_rate-tmp_bas426.gif
Internal Oscillator
Figure 36. Data Rate Error vs Temperature
ADS1246 ADS1247 ADS1248 tc_histo_idac_mismatch_bas426.gif
Figure 38. IDAC Mismatch Histogram
ADS1246 ADS1247 ADS1248 tc_idac_drift_bas426.gif
Figure 40. IDAC Drift
ADS1246 ADS1247 ADS1248 tc_idac_compliance1_bas453.png
Figure 42. IDAC Voltage Compliance
ADS1246 ADS1247 ADS1248 tc_digital-data_rate_bas426.gif
Figure 44. Digital Supply Current vs Data Rate
ADS1246 ADS1247 ADS1248 tc_digital-tmp_bas426.gif
Figure 46. Digital Supply Current vs Temperature
ADS1246 ADS1247 ADS1248 tc_digi_cur-tmp_bas426.gif
Figure 48. Digital Supply Current vs Temperature