9.3.1.1 EMI Filter

An RC filter at the input acts as an EMI filter on all channels. The –3-dB filter bandwidth is approximately 3 MHz.

9.3.1.2 Analog Input Structure

The analog input of the ADS129x is shown in Figure 24.

Figure 24. Analog Input Protection Circuit

9.3.1.3 Input Multiplexer

The ADS129x input multiplexers are very flexible and provide many configurable signal-switching options. Figure 25 shows the multiplexer on a single channel of the device. The device has eight blocks, one for each channel. TEST_PACE_OUT1, TEST_PACE_OUT2, and RLD_IN are common to all eight blocks. VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and subsystem diagnostics, calibration, and configuration. Select the switch settings for each channel by writing 1 to the appropriate values to the CHnSET[2:0] register (see the CHnSET register for details) and the RLD_MEAS bit in the CONFIG3 register (see the CONFIG3 register for details). More details of the ECG-specific features of the multiplexer are presented in the Input Multiplexer (Rerouting The Right Leg Drive Signal) subsection of the ECG-Specific Functions section.

1. MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section.

Figure 25. Input Multiplexer Block for One Channel

9.3.1.3.4 Temperature Sensor (TempP, TempN)

The ADS129x contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in Figure 26. The difference in current densities of the diodes yields a difference in voltage that is proportional to absolute temperature.

Figure 26. Measurement of the Temperature Sensor in the Input

As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal sensor tracks the PCB temperature closely. Self-heating of the ADS129x causes a higher reading than the temperature of the surrounding PCB.

The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, scale the the temperature reading code to μV.

Equation 1.

9.3.1.4 Analog Input

The analog input to the ADS129x is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span between –V_REF to V_REF. The absolute range for INP and INN must be between AVSS – 0.3 V and AVDD + 0.3 V. See Table 13 for an explanation of the correlation between the analog input and the digital codes. As shown in Figure 27 and Figure 28, there are two general methods of driving the analog input of the ADS129x: single-ended or differential. INP and INN are 180° out-of-phase in the differential input method. When the input is single-ended, the INN input is held at the common-mode voltage (CM), preferably at midsupply. The INP input swings around the same common-mode voltage and the peak-to-peak amplitude swings from CM – V_REF to CM + V_REF. When the input is differential, the common-mode is given by (INP + INN) / 2. Both the INP and INN inputs swing from CM + ½ V_REF to CM – ½ V_REF. For optimal performance, use the ADS129x devices in a differential configuration.

Figure 27. Methods of Driving the ADS129x: Single-Ended or Differential

Figure 28. Using the ADS129x in Single-Ended and Differential Input Modes

9.3.1.5 PGA Settings and Input Range

The PGA is a differential input and differential output amplifier, as shown in Figure 29. The PGA has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that are set by writing to the CHnSET register (see the CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 00h) section). The ADS129x have CMOS inputs, and therefore have negligible current noise. Table 5 shows the typical values of bandwidths for various gain settings. Table 5 shows the small-signal bandwidth.

Figure 29. PGA Implementation

The resistor string of the PGA that implements the gain has 120 kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input.

9.3.1.5.1 Input Common-Mode Range

The usable input common-mode range of the front end depends on various parameters, including the maximum differential input signal, supply voltage, PGA gain, and more. This range is described in Equation 2:

Equation 2.

where

• V_{MAX_DIFF} = maximum differential signal at the input of the PGA
• CM = common-mode range

For example, If V_DD = 3 V, gain = 6, and V_{MAX_DIFF} = 350 mV, then 1.25 V < CM < 1.75 V.

9.3.1.5.2 Input Differential Dynamic Range

The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This range is shown in Equation 3.

Equation 3.

The 3-V supply, with a reference of 2.4 V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300 mV. For higher dynamic range, use a 5-V supply with a reference of 4 V (set by the VREF_4V bit of the CONFIG3 register) to increase the differential dynamic range.

9.3.1.5.3 ADC Delta-Sigma Modulator

Each channel of the ADS129x has a 24-bit, delta-sigma ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of f_MOD = f_CLK / 4 for high-resolution (HR) mode and f_MOD = f_CLK / 8 for low-power (LP) mode. As in the case of any delta-sigma modulator, the noise of the ADS129x is shaped until f_MOD / 2, as shown in Figure 30. Use the on-chip digital decimation filters, explained in the Digital Decimation Filter section, to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the delta-sigma converters drastically reduces the complexity of the analog antialiasing filters that are typically needed with Nyquist ADCs.

Figure 30. Modulator Noise Spectrum up to 0.5 × f_MOD

9.3.1.6 Reference

Figure 31 shows a simplified block diagram of the ADS129x internal reference. The reference voltage is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS.

1. For V_REF = 2.4 V: R1 = 12.5 kΩ, R2 = 25 kΩ, and R3 = 25 kΩ. For V_REF = 4 V: R1 = 10.5 kΩ, R2 = 15 kΩ, and R3 = 35 kΩ.

Figure 31. Internal Reference

The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG systems, choose capacitor values with a bandwidth that is limited to less than 10Hz, so that the reference noise does not dominate the system noise. When using a 3-V analog supply, set the internal reference to 2.4 V. For a 5-V analog supply, set the internal reference to 4 V by setting the VREF_4V bit in the CONFIG2 register.

Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 32 shows a typical external reference drive circuitry. Power down is controlled by the PD_REFBUF bit in the CONFIG3 register. By default, the device wakes up in external reference mode.

Figure 32. External Reference Driver

9.3.1.7 ECG-Specific Functions

9.3.1.7.1 Input Multiplexer (Rerouting The Right Leg Drive Signal)

The input multiplexer has ECG-specific functions for the right leg drive (RLD) signal. The RLD signal is available at the RLDOUT pin after the appropriate channels are selected for the RLD derivation, feedback elements are installed external to the chip, and the loop is closed. This signal can be fed after filtering, or fed directly into the RLDIN pin as shown in Figure 33. Multiplex the RLDIN signal into any one of the input electrodes by setting the mux bits of the appropriate channel set registers to 110 for P-side or 111 for N-side. Figure 33 shows the RLD signal generated from channels 1, 2, and 3 routed to the N-side of channel 8. Use this feature to dynamically change the electrode that is used as the reference signal to drive the patient body. The corresponding channel cannot be used and can be powered down.

1. Typical values for example only.

Figure 33. Example of RLDOUT Signal Configured to be Routed to IN8N

9.3.1.7.2 Input Multiplexer (Measuring The Right Leg Drive Signal)

The RLDOUT signal can also be routed to a channel (that is not used for the calculation of RLD) for measurement. Figure 34 shows the register settings to route the RLDIN signal to channel 8. The measurement is done with respect to the voltage on the RLDREF pin. If RLDREF is set to internal, it is at (AVDD + AVSS) / 2. This feature is useful for debugging purposes during product development.

1. Typical values for example only.

Figure 34. RLDOUT Signal Configured to be Read Back by Channel 8

9.3.1.7.3 Wilson Central Terminal (WCT) and Chest Leads

In the standard 12-lead ECG, WCT voltage is defined as the average of right arm (RA), left arm (LA), and left leg (LL) electrodes. This voltage is used as the reference voltage for the measurement of the chest leads. The ADS129x has three integrated low-noise amplifiers that generate the WCT voltage. Figure 35 shows the block diagram of the implementation.

Figure 35. WCT Voltage

These devices provide the flexibility to route any one of the eight signals (IN1P to IN4N) to each of the amplifiers to generate the average. This flexibility allows the RA, LA, and LL electrodes to be connected to any input of the first four channels, depending on the lead configuration.

Each of the three amplifiers in the WCT circuitry can be powered down individually with register settings. By powering up two amplifiers, the average of any two electrodes is generated at the WCT pin. Powering up one amplifier provides the buffered electrode voltage at the WCT pin. The WCT amplifiers have limited drive strength, and thus, should be buffered if used to drive a low-impedance load.

Table 6 shows the typical WCT performance when using any 1, 2, or 3 of the WCT buffers.

Table 6. Typical WCT Performance

PARAMETER	ANY ONE (A, B, or C)	ANY TWO (A+B, A+C, or B+C)	ALL THREE (A+B+C)	UNIT
Integrated noise	540	382	312	nVRMS
Power	53	59	65	μW
–3-dB BW	30	59	89	kHz
Slew rate	BW limited	BW limited	BW limited	V/μs

As shown in Table 6, the overall noise reduces when more than one WCT amplifier is powered up. This noise reduction is a result of the fact that noise is averaged by the passive summing network at the output of the amplifiers. Powering down individual buffers gives negligible power savings because a significant portion of the circuitry is shared between the three amplifiers. The bandwidth of the WCT node is limited by the RC network. The internal summing network consists of three 30-kΩ resistors and a 80-pF capacitor. For optimal performance, add an external 100-pF capacitor. The effective bandwidth depends on the number of amplifiers that are powered up, as shown in Table 6.

Only use the WCT node to drive very high input impedances (typically greater than 500 MΩ). A typical application connects this WCT signal to the negative inputs of a ADS129x for use as a reference signal for the chest leads.

As mentioned, all three WCT amplifiers can be connected to one of eight analog input pins. The inputs of the amplifiers are chopped, and the chop frequency varies with the data rates of the ADS129x. The chop frequency for the three highest data rates scale 1:1. For example, at a 32-kSPS data rate, the chop frequency is 32 kHz in HR mode with WCT_CHOP = 0. The chop frequency of the four lower data rates is fixed at 4 kHz. When WCT_CHOP = 1, the chop frequency is fixed to highest data rate frequency (that is, f_MOD / 16), as shown in Table 7. The chop frequency appears at the output of the WCT amplifiers as a small square wave riding on dc. The amplitude of the square wave is the offset of the amplifier and is typically 5 mV_PP. As a result of out-of-band chopping, this artifact does not interfere with ECG-related measurements. As a result of the chopping function, the input current leakage on the pins with the connected WCT amplifiers increases at higher data rates and as the input common voltage swings closer to 0 V (AVSS), as described in Figure 36.

If the output of a channel connected to the WCT amplifier (for example, the V-lead channels) is connected to one of the pace amplifiers for external pace detection, the chopping artifact appears at the pace amplifier output.

Figure 36. WCT Input Leakage Current vs Input Voltage (WCT_CHOP = 0)

Figure 37. WCT Input Leakage Current vs Input Voltage (WCT_CHOP = 1)

Table 7. WCT Amplifiers Chop Frequency

CONFIG1.DR[2:0] BIT	CONFIG2.WCT_CHOP = 0	CONFIG2.WCT_CHOP = 1
000	fMOD/16	fMOD/16
001	fMOD / 32	fMOD / 16
010	fMOD / 64	fMOD / 16
011	fMOD / 128	fMOD / 16
100	fMOD / 128	fMOD / 16
101	fMOD / 128	fMOD / 16
110	fMOD / 128	fMOD / 16

9.3.1.7.3.1 Augmented Leads

In a typical implementation of the 12-lead ECG with eight channels, the augmented leads are calculated digitally. In certain applications, it may be required that all leads are derived in analog rather than digital. The ADS1298 and ADS1298R provide the option to generate the augmented leads by routing appropriate averages to channels 5, 6, and 7. The same three amplifiers that are used to generate the WCT signal are also used to generate the Goldberger central terminal (GCT) signals. Figure 38 shows an example of generating the augmented leads in analog domain. In this implementation, more than eight channels are used to generate the standard 12 leads. This feature is not available in the ADS1294, ADS1294R, ADS1296 and ADS1296R.

Figure 38. Analog Domain Augmented Leads

9.3.1.7.3.2 Right Leg Drive with the WCT Point

In certain applications, the out-of-phase version of the WCT is used as the RLD reference. The ADS1298 provides the option to have a buffered version of the WCT terminal at the RLD_OUT pin. This signal can be inverted in phase using an external amplifier and then used as the right leg drive. Refer to the Right Leg Drive (RLD DC Bias Circuit) section for more details.

9.3.1.7.4 Lead-Off Detection

Patient electrode impedances decay over time; therefore, these electrode connections must be continuously monitored to verify that a suitable connection is present. The ADS129x lead-off detection functional block provides significant flexibility to choose from various lead-off detection strategies. Although called lead-off detection, this feature is in fact electrode-off detection.

The basic principle is to inject an excitation signal and measure the response to determine if the electrode is off. As shown in the lead-off detection functional block diagram in Figure 39, this circuit provides two different methods of determining the state of the patient electrode. The methods differ in the frequency content of the excitation signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENSP and LOFF_SENSN registers. The internal excitation circuitry can be disabled while the sensing circuitry is enabled.

Figure 39. Lead-Off Detection

9.3.1.7.4.1 DC Lead-Off

In this approach, the lead-off excitation is accomplished with a dc signal. Choose a dc excitation signal from either a pullup or pulldown resistor, or from a current source or sink system, as shown in Figure 40. Select by setting the VLEAD_OFF_EN bit in the LOFF register. One side of the channel is pulled to supply, and the other side is pulled to ground. Swap the pullup resistor and pulldown resistor by setting the bits in the LOFF_FLIP register, as shown in Figure 41. If using a current source or sink, set the magnitude of the current by using the ILEAD_OFF[1:0] bits in the LOFF register. The current source or sink gives larger input impedance compared to the 10-MΩ pullup or pulldown resistor.

Figure 40. DC Lead-Off Excitation Options

Figure 41. LOFF_FLIP Usage

Response sensing is achieved either by looking at the digital output code from the device, or by monitoring the input voltages with on-chip comparators. If either of the electrodes is off, the pullup or pulldown resistors saturate the channel. Look at the output code to determine if either the P-side or the N-side is off. To pinpoint which side is off, check the comparator outputs. During conversion, the input voltage is simultaneously monitored by using a comparator and a 4-bit DAC with levels that are set by the COMP_TH[2:0] bits in the LOFF register. The comparator outputs are stored in the LOFF_STATP and LOFF_STATN registers. These two registers are available as a part of the output data stream (see the Data Output Pin (DOUT) section). If dc lead-off is not used, the lead-off comparators can be powered down by setting the PD_LOFF_COMP bit in the CONFIG4 register.

An example procedure to turn on dc lead-off is given in the Lead-Off section.

9.3.1.7.4.2 AC Lead-Off

This method uses an out-of-band ac signal for excitation. The ac signal is generated by providing pullup and pulldown resistors at the input with a fixed frequency. The ac signal is passed through an antialiasing filter to prevent aliasing. Select the frequency with the FLEAD_OFF[1:0] bits in the LOFF register. The excitation frequency is a function of the output data rate and is f_DR / 4. This out-of-band excitation signal is passed through the channel and measured at the output.

AC signal sensing is achieved by passing the signal through the channel to digitize the signal, and measuring the output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of the excitation signal at the output spectrum, the lead-off status is calculated. Therefore, the ac lead-off detection is accomplished simultaneously with the ECG signal acquisition.

9.3.1.7.5 RLD Lead-Off

Determine if the RLD electrode is connected in the ADS129x by powering down the RLD amplifier. After power down, there are two measurement procedures to determine the RLD electrode connect status: a pullup or pulldown resistor, or a sink or source current source, as shown in Figure 42. Set the reference level of the comparator to determine the acceptable RLD impedance threshold.

Figure 42. RLD Lead-Off Detection at Power Up

The current source, or pullup or pulldown resistor method has no function when the RLD amplifier is powered on. Use the comparator to sense the voltage at the output of the RLD amplifier. The comparator threshold is set by the same LOFF[7:5] bits that are used to set the thresholds for the other negative inputs.

9.3.1.7.6 Right Leg Drive (RLD) DC Bias Circuit

Use the right leg drive (RLD) circuitry to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode voltage of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow range, depending on the loop gain. Stabilizing the entire loop is specific to the individual system, based on the various poles in the loop. The ADS129x incorporate muxes that are used to select the channel to the operational amplifier. All the amplifier terminals are available at the pins, allowing selection of the components for the feedback loop. The circuit shown in Figure 43 shows the overall functional connectivity for the RLD bias circuit.

Set the reference voltage for the RLD to be generated internally ([AVDD + AVSS] / 2), or provided externally with a resistive divider. The selection of an internal versus external reference voltage for the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the CONFIG3 register.

If the RLD function is not used, power down the amplifier using the PD_RLD bit (see the CONFIG3: Configuration Register 3 (address = 03h) (reset = 40h) section for details). This bit is also used in daisy-chain mode to power down all but one of the RLD amplifiers.

The functionality of the RLDIN pin is explained in the Input Multiplexer section. An example procedure to use the RLD amplifier is shown in the Right Leg Drive section of the Power-Supply Recommendations.

1. Typical values.

2. When CONFIG3 bit RLDREF_INT = 0, the RLDREF_INT switch is closed and the RLDREF_INT switch is open. When CONFIG3 bit RLDREF_INT = 1, the RLDREF_INT switch is open and the RLDREF_INT switch is closed.

Figure 43. RLD Channel Selection2⁽²⁾

9.3.1.7.6.1 WCT as RLD

In certain applications, the RLD is derived as the average of RA, LA, and LL. This level is the same as the WCT voltage. The WCT amplifier has limited drive strength; therefore, only use the WCT to drive very high impedances directly. The ADS129x provide an option to internally buffer the WCT signal by setting the WCT_TO_RLD bit in the CONFIG4 register. Short the RLD_OUT and RLD_INV pins external to the device. Before the RLD_OUT signal is connected to the RLD electrode, use an external amplifier to invert the phase of the signal for negative feedback.

Figure 44. Using the WCT as the Right Leg Drive (RLD)

9.3.1.7.6.2 RLD Configuration with Multiple Devices

Figure 45 shows multiple devices connected to an RLD.

Figure 45. RLD Connection for Multiple Devices

9.3.1.7.7 Pace Detect

The ADS129x provide flexibility for pace detection by using either software or external hardware. The software approach is made possible by providing sampling rates up to 32 kSPS. The external hardware approach is made possible by bringing out the output of the PGA at two pins: TESTP_PACE_OUT1 and TESTN_PACE_OUT2. If the WCT amplifier is connected to the signal path, switching noise occurs as a result of chopping; see the Wilson Central Terminal (WCT) and Chest Leads section for details.

9.3.1.7.7.1 Software Approach

To use the software approach, operate the device at 8 kSPS or more to capture the fastest pulse. Afterwards, digital signal processing is used to identify the presence of the pacemaker pulse. The software approach gives the utmost flexibility to program the pace detect threshold on-the-fly (dynamically) using software. This flexibility is increasingly important as pacemakers evolve over time. Two parameters must be considered while measuring fast pace pulses:

1. PGA bandwidth: determines the gain setting that can be used; shown in Table 5.
2. Settling time: determines the operating data rate for the device. For a step change in input, the digital decimation filter takes 3 × t_DR to settle.

9.3.1.7.7.2 External Hardware Approach

One of the drawbacks of using the software approach is that all channels on a single device must operate at higher data rates. For systems where high data rates are a problem, the ADS129x provide the option of connecting external hardware to the output of the PGA to detect the presence of the pulse. The output of the pace detection logic is then fed into the device through one of the GPIO pins. The GPIO data are transmitted through the SPI port and loaded 2 t_CLKs before DRDY goes low. Two of the eight channels are selected using register bits in the PACE register: one from the odd-numbered channels, and the other from the even-numbered channels. During the differential to single-ended conversion, there is an attenuation of 0.4; therefore, the total gain in the pace path is equal to (0.4 × PGA_GAIN). The pace output signals are multiplexed with the TESTP and TESTN signals through the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins, respectively. Channel selection is achieved by setting bits[4:1] of the PACE register. If the pace circuitry is not used, turn off the pace amplifiers by using the PD_PACE bit in the PACE register.

If the output of a channel connected to the WCT amplifier (for example, the V-lead channels) is connected to one of the pace amplifiers for external pace detection, chopping artifacts appear at the pace amplifier output. See the Wilson Central Terminal (WCT) and Chest Leads section for more details.

1. GPIO1 can be used as the PACE_IN signal.

Figure 46. Hardware Pace Detection Option

9.3.1.7.8 Respiration

As shown in Table 8, the ADS129xR provide three options for respiration impedance measurement: external respiration, internal respiration using on-chip modulation signals, and internal respiration using user-generated modulation signals. The ADS129x provides only external respiration impedance measurement.

Table 8. Respiration Control

RESP.RESP_CTRL[1]	RESP.RESP_CTRL[0]	DESCRIPTION	MODE AVAILABLE
0	0	Respiration disabled	ADS129x, ADS129xR
0	1	Generates modulation and demodulation signals for external respiration circuitry. RESP_CLK signals on GPIO2, GPIO3, and GPIO4.	ADS129x, ADS129xR
1	0	Respiration measurement using internally-generated RESP_MOD signals.	ADS129xR
1	1	Respiration measurement using user-generated modulation and blocking signal.	ADS129xR(1)

(1) Do not set RESP_CTRL[1:0] = 11 if CLKSEL = 1 (internal master clock).

For more information on respiration impedance measurement, see Respiration Rate Measurement Using Impedance Pneumography, SBAA181.

9.3.1.7.8.1 External Respiration Circuitry (RESP_CTRL = 01b)

With this option, GPIO2, GPIO3, and GPIO4 are automatically configured as outputs. The phase relationship between the signals is shown in Figure 47. GPIO2 is the exclusive-OR of GPIO3 and GPIO4, as shown in Figure 48. GPIO3 is the modulation signal, and GPIO4 is the demodulation signal. While using this option, the general-purpose pin functions of GPIO2, GPIO3, and GPIO4 are not available. The modulation frequency is set to either 64 kHz or 32 kHz by using the RESP_FREQ[2:0] bits in the CONFIG4 register. The remaining bit options of RESP_FREQ[2:0] generate square waves on GPIO3 and GPIO4. The exclusive-OR out on GPIO2 is only available in 64-kHz or 32-kHz. The phase of GPIO4, relative to GPIO3, is set by RESP_PH[2:0] bits in the RESP register.

Use this option to implement custom respiration impedance circuitry external to the ADS129x.

Figure 47. External Respiration (RESP_CTRL = 01b) Timing

Figure 48. External Respiration (RESP_CTRL = 01b) Block Diagram

Table 9. Switching Characteristics for Figure 47⁽¹⁾

PARAMETER		2.7 V ≤ DVDD ≤ 3.6 V			1.65 V ≤ DVDD ≤ 2 V			UNIT
		MIN	TYP	MAX	MIN	TYP	MAX
tPHASE	Respiration phase delay, set by RESP.RESP_PH[2:0]	22.5		157.5	22.5		157.5	Degrees
tBLKDLY	Modulation clock rising edge to XOR signal		1			5		ns

(1) Specifications apply from –40°C to 85°C.

9.3.1.7.8.2 Internal Respiration Circuitry with Internal Clock (RESP_CTRL = 10b, ADS129xR Only)

Figure 49 shows a block diagram of the internal respiration circuitry. The internal modulation and demodulator circuitry can be selectively used.

The modulation block is controlled by the RESP_MOD_EN bit and the demodulation block is controlled by the RESP_DEMOD_EN bit. The modulation signal is a square wave of magnitude VREFP – AVSS. Using this option, the output of the modulation circuitry is available at the RESP_MODP and RESP_MODN pins of the device. This availability allows custom filtering to be added to the square-wave modulation signal. Using this option, GPIO2, GPIO3, and GPIO4 can be used for other purposes. The modulation frequency is either 64 kHz or 32 kHz, as set by the RESP_FREQ[2:0] bits in the CONFIG4 register. The phase of the internal demodulation signal is set by the RESP_PH[2:0] bits in the RESP register.

When this respiration option is enabled, ADS129xR channel 1 cannot be used to acquire ECG signals. If the RA and LA leads are intended to measure respiration and ECG signals, wire the two leads into channel 1 for respiration and channel 2 for ECG signals.

Figure 49. Internal Respiration Block Diagram

9.3.1.7.8.3 Internal Respiration Circuitry With User-Generated Signals (RESP_CTRL = 11b, ADS129xR Only)

In this mode GPIO2, GPIO3, and GPIO4 are automatically configured as inputs and cannot be used for other purposes. The signals must be provided as described in Figure 50. Do not use the internal master clock in this mode.

Figure 50. Internal Respiration (RESP_CTRL = 11b) Timing Diagram

Table 10. Swtiching Characteristics for Figure 50⁽¹⁾

PARAMETER		1.65 V ≤ DVDD ≤ 3.6V			UNIT
		MIN	TYP	MAX
tPHASE	Respiration phase delay	0		157.5	Degrees
tBLKDLY	Modulation clock rising edge to XOR signal		0	5	ns

(1) Specifications apply from –40°C to 85°C.

9.3.2.1 GPIO Pins (GPIO[4:1])

The ADS129x have a total of four general-purpose digital input/output (GPIO) pins available in normal operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits of the GPIO register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the GPIOD bit sets the output value.

If configured as inputs, these pins must be driven; do not float these pins. The GPIO pins are set as inputs after power-on or after a reset. Figure 51 shows the GPIO port structure. If not used, short these pins to DGND.

For example, one configuration is to use GPIO1 as the PACEIN signal, multiplex GPIO2 with RESP_BLK signal, multiplex GPIO3 with the RESP signal, and multiplex GPIO4 with the RESP_PH signal.

Figure 51. GPIO Port Pin

9.3.2.2 Power-Down Pin (PWDN)

When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wakeup. During power down, shut down the external clock to save power.

9.3.2.3 Reset (RESET Pin and Reset Command)

There are two methods to reset the ADS129x: pull the RESET pin low, or send the RESET opcode command (see the RESET: Reset Registers to Default Values section). Take the RESET pin low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. At reset, 18 t_CLK cycles are required to complete initialization of the configuration registers to the default states and start the conversion cycle. For more information, see the RESET: Reset Registers to Default Values section. An internal reset is automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to new values with a WREG command.

9.3.2.4 Digital Decimation Filter

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs are made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in ECG applications to implement software pace detection and ac lead-off detection.

The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters is adjusted by the DR bits in the CONFIG1 register (see Table 16 for details). This setting is a global setting that affects all channels; therefore, in these devices, all channels operate at the same data rate.

9.3.2.4.1 Sinc Filter Stage (sinx / x)

The sinc filter is a variable-decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of f_MOD. The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter.

Equation 4 shows the scaled Z-domain transfer function of the sinc filter.

Equation 4.

The frequency-domain transfer function of the sinc filter is shown in Equation 5.

Equation 5.

where

• N = decimation ratio

The sinc filter has notches (or zeroes) that occur at the output data rate multiples. At these frequencies, the filter has infinite attenuation. Figure 52 shows the frequency response of the sinc filter and Figure 53 shows the rolloff of the sinc filter. With a step change at input, the filter requires 3 × t_DR conversion cycles to settle. After a rising edge of the START pin or completion of the START command, the filter takes t_SETTLE periods to give the first data output. The settling time of the filters at various data rates are discussed in the Start Mode subsection of the SPI Interface section. Figure 54 and Figure 55 show the filter transfer function to f_MOD / 2 and f_MOD / 16, respectively, at different data rates. Figure 56 shows the transfer function extended out to 4 × f_MOD. As shown in the figures, the passband of the ADS129x repeats itself at every f_MOD muiltple. Choose input R-C antialiasing filters for the system that sufficiently attenuate any interference in frequencies around multiples of f_MOD.

Figure 52. Sinc Filter Frequency Response

Figure 54. Transfer Function of On-Chip Decimation Filters to f_MOD / 2

Figure 56. Transfer Function of On-Chip Decimation Filters
to 4 × f_MOD for DR[2:0] = 000 and DR[2:0] = 110

Figure 53. Sinc Filter Roll-Off

Figure 55. Transfer Function of On-Chip Decimation Filters to f_MOD / 16

9.3.2.5 Clock

The ADS129x provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. The accuracy varies over the specified temperature range; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.

Use the CLKSEL pin to select either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 11. Use the CLK_EN bit is when multiple devices are connected in a daisy-chain configuration. During power down, shut down the external clock to save power.

9.4.1.1 Start Mode

Pull the START pin high for at least 2 t_CLK periods, or send the START command to begin conversions. When the START pin is low, or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).

When using the START opcode to begin conversions, hold the START pin low. The ADS129x feature two modes to control conversion: continous and single-shot. The mode is selected by SINGLE_SHOT (bit 3 of the CONFIG4 register). In multiple device configurations, the START pin is used to synchronize devices (see the Multiple-Device Configurationsection for more details).

9.4.1.1.1 Settling Time

The settling time (t_SETTLE) is the time it takes for the converter to output fully-settled data when the START signal is pulled high.

When the START pin is pulled high, or when the START command is sent, the device ADCs convert the input signals and DRDY is pulled high. The next falling edge of DRDY indicates that data are ready. Figure 57 shows the timing diagram and Table 12 shows the settling time for different data rates as a function of t_CLK. The settling time depends on f_CLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register).

Figure 57. Settling Time for Initial Conversion

Table 12. Settling Times for Different Data Rates (t_SETTLE)

DR[2:0]	SETTLING TIME (tCLK Periods)
	HIGH-RESOLUTION MODE	LOW-POWER MODE
000	296	584
001	584	1160
010	1160	2312
011	2312	4616
100	4616	9224
101	9224	18440
110	18440	36872

When the START pin is held high and there is a step change in the input signal, 3 × t_DR conversion cycles are required for the filter to settle to the new value, as shown in Figure 58. Settled data are available on the fourth DRDY pulse. This settling time must be considered when trying to measure narrow pace pulses for pace detection. Data are available to read at each DRDY high-to-low transition, but can be ignored.

Figure 58. Settling Time for Input Transient

9.4.1.2 Data Ready Pin (DRDY)

DRDY is an output. When DRDY transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. Regardless of the status of the CS signal, a rising edge on SCLK pulls DRDY high. Thus, when using multiple devices in the SPI bus, gate SCLK with CS. The behavior of DRDY depends on if the device is in RDATAC mode or if the RDATA command is being used to read data on demand. See the RDATAC: Read Data Continuous and RDATA: Read Datasections for further details.

When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption.

Use the START pin or the START command to place the device either in normal data capture mode or pulse data capture mode.

Figure 59 shows the relationship among DRDY, DOUT, and SCLK during data retrieval (in the case of an ADS129x with a selected data rate that gives 24-bit resolution). DOUT latches at the rising edge of SCLK. The device pulls DRDY high at the first falling edge of SCLK, regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. The data starts from the MSB of the status word and then proceeds to the ADC channel data in sequential order (that is, channel 1, channel 2, ..., channel x). Channels that are powered down still have a position in the data stream; however, the data are not valid and can be ignored.

Figure 59. DRDY with Data Retrieval (CS = 0)

The DRDY signal is cleared on the first SCLK falling edge, regardless of the state of CS. Even if no data are clocked out, the DRDY signal is still cleared. Take this condition into consideration if the SPI bus is used to communicate with other devices on the same bus. Figure 60 shows a timing diagram for this multiplexing.

Figure 60. DRDY and SCLK Behavior for SPI Bus Multiplexing

9.4.1.3 Data Retrieval

Data retrieval is accomplished in one of two methods:

1. RDATAC: the read data continuous command sets the device mode that reads data continuously without sending opcodes. See the RDATAC: Read Data Continuous section for more details.
2. RDATA: the read data command reads just one data output from the device. See the RDATA: Read Data section for more details.

The conversion data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. Keep DIN low for the entire read operation.

9.4.1.3.1 Status Word

The ADS129x data readback is preceded by a status word that provides information on the state of the ADC. The status word is 24 bits long and contains the values for LOFF_STATP, LOFF_STATN, and part of the GPIO registers. The content alignment is shown in Figure 61.

Figure 61. Status Word Content

9.4.1.4 Single-Shot Mode

Enable single-shot mode by setting the SINGLE_SHOT bit in CONFIG4 register to 1. In single-shot mode, the ADS129x perform a single conversion when the START pin is taken high, or when the START opcode command is sent. As seen in Figure 62, when a conversion completes, DRDY goes low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To begin a new conversion, take the START pin low and then back high for at least two t_CLKs, or transmit the START opcode again. When switching from continous conversion mode to single-shot mode, make sure the START signal is pulsed, or issue a STOP command followed by a START command.

Figure 62. DRDY With No Data Retrieval in Single-Shot Mode

Single-shot conversion mode is provided for applications that require nonstandard or noncontinuous data rates. Issue a START command or toggle the START pin high to reset the digital filter, effectively dropping the data rate by a factor of four. This mode leaves the system more susceptible to aliasing effects, thus requiring more complex analog or digital filtering. Loading on the host processor increases because it must toggle the START pin or send a START command to initiate a new conversion cycle.

9.4.1.5 Continuous Conversion Mode

Conversions begin when the START pin is taken high for at least two t_CLKs, or when the START opcode command is sent. As seen in Figure 63, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete. Figure 64 and Table 14 show the required timing of DRDY to the START pin and the START and STOP opcode commands when controlling conversions in this mode. To keep the converter running continuously, permanently tie the START pin high. When switching from single-shot mode to continous-conversion mode, pulse the START signal or a issue a STOP command followed by a START command. This conversion mode is ideal for applications that require a continuous stream of conversions results.

1. START and STOP opcode commands take effect on the seventh SCLK falling edge.

Figure 63. Continuous Conversion Mode

1. START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.

Figure 64. START to DRDY Timing

9.4.2.1 Cascade Configuration

Figure 66(a) shows a configuration with two devices cascaded together. One of the devices is an ADS1298 (eight channels) and the other is an ADS1294 (four channels). Together, they create a system with 12 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the majority of applications.

9.4.2.2 Daisy-Chain Configuration

Enable daisy-chain mode by setting the DAISY_EN bit in the CONFIG1 register. Figure 66(b) shows the daisy-chain configuration. In this configuration, SCLK, DIN, and CS are shared across multiple devices. Connect the DOUT pin of the first device to the DAISY_IN pin of the next device, thereby creating a chain. Issue one extra SCLK between each data set. Note that when using daisy-chain mode, the multiple readback feature is not available. Short the DAISY_IN pin to digital ground if not used. Figure 2 describes the required timing for the ADS1298 shown in Figure 67. Data from the ADS1298 appear first on DOUT, followed by a don’t care bit, and finally by the status and data words from the ADS1294.

1. To reduce pin count, set the START pin low and use the START opcode command to synchronize and start conversions.

Figure 66. Multiple Device Configurations

Figure 67. Daisy-Chain Timing for Figure 66(b)

Important reminders when using daisy-chain mode:

1. Issue one extra SCLK between each data set (see Figure 67).
2. All devices are configured to the same register values because CS is shared.
3. Device register readback (RREG) is only valid for device 0 in the daisy chain. Only conversion data can be read from device 1 to device N, where N is the last device in the chain; register data cannot be read.

If all devices in the chain operate in the same register setting, DIN can be shared, thereby reducing the SPI communication signals to four, regardless of the number of devices. However, the individual devices cannot be programmed; therefore, the RLD driver cannot be shared among the multiple devices. Furthermore, an external clock must be used.

As shown in Figure 2, the SCLK rising edge shifts data out of the ADS129x on DOUT. The SCLK rising edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK rate speed, but it also makes the interface sensitive to board-level signal delays. The more devices in the chain, the more challenging it becomes to adhere to setup and hold times. A star-pattern connection of SCLK to all devices, minimizing length of DOUT, and other PCB layout techniques help. Placing delay circuits such as buffers between DOUT and DAISY_IN is another way to mitigate this challenge. One other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. In addition, note that daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries.

The maximum number of daisy-chained devices depends on the data rate at which the device is operated. The maximum number of devices can be estimated with Equation 6:

Equation 6.

where

• N_BITS = device resolution (depends on data rate)
• N_CHANNELS = number of channels in the device (4, 6, or 8)

For example, when the ADS1298 (eight-channel, 24-bit version) is operated at a 2-kSPS data rate with a 4-MHz f_SCLK, up to ten devices can be daisy-chained.

9.5.1.1 Chip Select Pin (CS)

Chip select (CS) selects the ADS129x devices for SPI communication. While CS is low, the serial interface is active. CS must remain low for the entire duration of the serial communication. After the serial communication is finished, always wait four or more t_CLK periods before taking CS high. When CS is taken high, the serial interface resets, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low.

While ADS129x is selected, the device attempts to decode and execute commands every eight serial clocks. If the device ceases to execute serial commands, it is possible extra clock pulses were presented that placed the serial interface into an unknown state. To reset the serial interface to a known state, take CS high and back low again.

9.5.1.2 Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from the device. The serial clock (SCLK) features a Schmitt-triggered input, and clocks data on the DIN and DOUT pins into and out of the ADS129x. Even though the input has hysteresis, keep SCLK as clean as possible to prevent glitches from accidentally forcing a clock event. The absolute maximum limit for SCLK is specified in the Timing Requirements: Serial Interface table.

While ADS129x is selected (CS = low), the device attempts to decode and execute commands every eight serial clocks. Therefore, present multiples of eight SCLKs every serial transfer to keep the interface in a normal operating mode. If the interface ceases to function because of extra serial clocks, reset by toggling CS high and back low.

For a single device, the minimum speed required for SCLK depends on the number of channels, number of bits of resolution, and output data rate. For multiple cascaded devices, see the Cascade Configuration section. Equation 7 shows the calculation for minimum SCLK speed.

For example, if the ADS1298 is used at 500-SPS (eight channels, 24-bit resolution), the minimum SCLK speed is 110 kHz.

Retrieve data either by putting the device in RDATAC mode or by issuing a RDATA command for data on demand. The SCLK rate limitation of Equation 7 also applies to RDATAC. For the RDATA command, the limitation applies if data must be read between two consecutive DRDY signals. Equation 7 assumes that there are no other commands issued between data captures.

9.5.1.2.1 SCLK Clocking Methods

As shown in Figure 68, there are two different SCLK clocking methods to satisfy the decode timing specification shown in Figure 1 for multiple-byte commands.

For SCLK speeds that meet the t_SDECODE timing requirement shown in Figure 1, transmit SCLK in a continuous stream when CS is low. This method is not to be confused with a free-running SCLK, where SCLK operates when CS is high. Free-running SCLK operation is not supported by this device.

For faster SCLK speeds that do not meet the t_SDECODE timing requirement, SCLK is transmitted in 8-bit bursts with a delay between bursts. The absolute maximum SCLK limit is specified in the Timing Requirements: Serial Interface table. Figure 68 shows the difference between the two SCLK clocking methods for this device.

Figure 68. SCLK Clocking Methods

9.5.1.3 Data Input Pin (DIN)

The data input pin (DIN) is used along with SCLK to communicate with the ADS129x (opcode commands and register data). The device latches data on DIN on the falling edge of SCLK.

9.5.1.4 Data Output Pin (DOUT)

The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS129x. Data on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available. Use this feature to minimize the number of connections between the device and the system controller.

Figure 69 shows the data output protocol for ADS1298.

Figure 69. SPI Bus Data Output for the ADS1298 (Eight Channels)

Table 15. Opcode Command Definitions

9.5.2.1 WAKEUP: Exit Standby Mode

The WAKEUP opcode exits low-power standby mode; see the STANDBY: Enter Standby Mode section. Time is required when exiting standby mode (see the Electrical Characteristics for details). There are no restrictions on the SCLK rate for this command; issue this command at any time. Any subsequent command must be sent after 4 t_CLK cycles.

9.5.2.2 STANDBY: Enter Standby Mode

The STANDBY opcode command enters low-power standby mode. All parts of the circuit are shut down except for the reference section. Standby mode power consumption is specified in the Electrical Characteristics. There are no restrictions on the SCLK rate for this command; issue this command at any time. Send a WAKEUP command to return device to normal operation. Serial interface is active; therefore, register read and write commands are permitted while in this mode.

9.5.2.3 RESET: Reset Registers to Default Values

The RESET command resets the digital filter cycle and returns all register settings to the respective default values. See the Reset (RESET Pin and Reset Command) section for more details. There are no restrictions on the SCLK rate for this command; issue this command at any time. 18 t_CLK cycles are required to execute the RESET command. Do not send any commands during this time.

9.5.2.4 START: Start Conversions

This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command, there must be a gap of 4 t_CLK cycles between the two commands. When the START opcode is sent to the device, keep the START pin low until the STOP command is issued. (See the Start Mode subsection of the SPI Interface section for more details.) There are no restrictions on the SCLK rate for this command and it can be issued any time.

9.5.2.5 STOP: Stop Conversions

The STOP opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command; issue this command at any time.

9.5.2.6 RDATAC: Read Data Continuous

The RDATAC opcode enables the output of conversion data on each DRDY without the need to issue subsequent read data opcodes. This opcode places the conversion data in the output register where it may be shifted out directly. The read data continuous mode is the default mode of the device and the device defaults to this mode on power up and reset.

RDATAC mode is cancelled by the stop read data continuous command (SDATAC). If the device is in RDATAC mode, an SDATAC command must be issued before any other commands can be sent to the device. There is no restriction on the SCLK rate for this command. However, subsequent data retrieval SCLKs or the SDATAC opcode command must wait at least 4 t_CLK cycles. As shown in Figure 70, the timing for RDATAC illustrates the keep-out zone of 4 t_CLK periods around the DRDY pulse when this command cannot be issued. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from the device after RDATAC command is issued, make sure that either the START pin is high or the START command is issued. Figure 70 shows the recommended way to use the RDATAC command. RDATAC is ideally suited for applications such as data loggers or recorders, where registers are set once and do not need to be reconfigured.

1. t_UPDATE = 4 / f_CLK (where f_CLK = 1 / t_CLK). Do not read data during this time.

Figure 70. RDATAC Usage

9.5.2.7 SDATAC: Stop Read Data Continuous

This SDATAC opcode command cancels read data continuous (RDATAC) mode. There is no restriction on the SCLK rate for this command, but the next command must wait for 4 t_CLK cycles.

9.5.2.8 RDATA: Read Data

Issue the RDATA command after DRDY goes low to read the conversion result (in SDATAC mode). There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make sure that either the START pin is high or the START command is issued. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 71 shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type systems, where register settings must be read or changed often between conversion cycles.

Figure 71. RDATA Usage

9.5.2.9 Sending Multibyte Commands

The ADS129x serial interface decodes commands in bytes, and requires 4 t_CLK periods to decode and execute. Therefore, when sending multibyte commands, a 4 t_CLK period must separate the end of one byte (or opcode) and the next.

For example, if CLK is 2.048 MHz, then t_SDECODE (4 × t_CLK) is 1.96 µs. When SCLK is 16 MHz, the maximum transfer speed for one byte is 500 ns. This byte transfer time does not meet the t_SDECODE specification; therefore, a delay must be inserted so that the end of the second byte arrives 1.46 µs later. However, if SCLK is 4 MHz, one byte is transferred in 2 µs. Because this transfer time exceeds the t_SDECODE specification, the processor can send subsequent bytes without delay. In the second scenario, the serial port can be programmed to use multiple-byte transfers instead of the single-byte transfers required to meet the timing of the first scenario .

9.5.2.10 RREG: Read From Register

The RREG opcode command reads register data. The RREG command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1.

First opcode byte: 001r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.

The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 72. When the device is in read data continuous mode, it is necessary to issue a SDATAC command before a RREG command can be issued. An RREG command can be issued any time. However, because this command is a multibyte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK)section for more details. CS must be low for the entire command.

Figure 72. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)
(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)

9.5.2.11 WREG: Write to Register

The WREG opcode command writes register data. The WREG command is a two-byte opcode followed by the input of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to write – 1.

First opcode byte: 010r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.

After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 73. The WREG command can be issued any time. However, because this command is a multibyte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) section for more details. CS must be low for the entire command.

Figure 73. WREG Command Example: Write Two Registers Starting from 00h (ID Register)
(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)

9.6.1.1 ID: ID Control Register (address = 00h) (reset = xxh)

9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) (reset = 06h)

9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) (reset = 40h)

Configuration register 2 configures the test signal generation. See the Input Multiplexer section for more details.

9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) (reset = 40h)

Configuration register 3 configures multireference and RLD operation.

9.6.1.5 LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)

The lead-off control register configures the lead-off detection operation.

9.6.1.6 CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 00h)

The CH[1:8]SET control register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels.

9.6.1.7 RLD_SENSP: RLD Positive Signal Derivation Register (address = 0Dh) (reset = 00h)

This register controls the selection of the positive signals from each channel for right leg drive (RLD) derivation. See the Right Leg Drive (RLD) DC Bias Circuit section for details.

Registers bits[5:4] are not available for the ADS1294 or ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R.

9.6.1.8 RLD_SENSN: RLD Negative Signal Derivation Register (address = 0Eh) (reset = 00h)

This register controls the selection of the negative signals from each channel for right leg drive derivation. See the Right Leg Drive (RLD) DC Bias Circuit section for details.

Registers bits[5:4] are not available for the ADS1294 and ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R.

9.6.1.9 LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)

This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection section for details. The LOFF_STATP register bits are only valid if the corresponding LOFF_SENSP bits are set to 1.

Registers bits[5:4] are not available for the ADS1294 or ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R.

9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)

This register selects the negative side from each channel for lead-off detection. See the Lead-Off Detectionsection for details. The LOFF_STATN register bits are only valid if the corresponding LOFF_SENSN bits are set to 1.

Registers bits[5:4] are not available for the ADS1294 or ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R.

9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)

This register controls the direction of the current used for lead-off derivation. See the Lead-Off Detectionsection for details.

9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)

This register stores the status of whether the positive electrode on each channel is on or off. See the Lead-Off Detection section for details. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits are not set to 1.

When the LOFF_SENSEP bits are 0, the LOFF_STATP bits should be ignored.

9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)

This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off Detection section for details. Ignore the LOFF_STATN values if the corresponding LOFF_SENSN bits are not set to 1.

When the LOFF_SENSEN bits are 0, the LOFF_STATP bits should be ignored.

9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)

The general-purpose I/O register controls the action of the three GPIO pins. When RESP_CTRL[1:0] is in mode 01 and 11, the GPIO2, GPIO3, and GPIO4 pins are not available for use.

9.6.1.15 PACE: Pace Detect Register (address = 15h) (reset = 00h)

This register provides the pace controls that configure the channel signal used to feed the external pace detect circuitry. See the Pace Detect section for details.

9.6.1.16 RESP: Respiration Control Register (address = 16h) (reset = 00h)

This register provides the controls for the respiration circuitry; see the Respiration section for details.

9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)

9.6.1.18 WCT1: Wilson Central Terminal and Augmented Lead Control Register (address = 18h) (reset = 00h)

The WCT1 control register configures the device WCT circuit channel selection and the augmented leads.

9.6.1.19 WCT2: Wilson Central Terminal Control Register (address = 18h) (reset = 00h)

The WCT2 configuration register configures the device WCT circuit channel selection.