SBAU460 April   2024 PCM1841-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Overview
    2. 2.2 Hardware Configuration
      1. 2.2.1 PCM1841Q1EVM Inputs
        1. 2.2.1.1 Line Inputs
        2. 2.2.1.2 Onboard Microphone Input
    3. 2.3 Power Supply
  9. 3Hardware Design Files
    1. 3.1 PCM1841Q1EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 PCM1841Q1EVM Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.3 Power Supply

The PCM1841Q1EVM can be powered with a single 5V power supply connected to J6. Onboard low dropout regulators convert the 5V supply to the 3.3V and 1.8V rails used by the ADC. The analog supply, AVDD, is fixed at 3.3V. The digital supply, IOVDD, can be set to either 1.8V or 3.3V with J5. A possibility is to power the ADC directly by removing J9 and J5 and applying a voltage directly to the AVDD and IOVDD test points. Note that if this is done, then this is important to keep J10 populated (or make sure there is a path between the pins if the supply current is being monitored) as this jumper connects the applied IOVDD to the mode selection pins and other circuitry that relies on IOVDD. If external supplies are used, then there is an onboard voltage supervisor, U3, that holds the ADC in shutdown until both AVDD and IOVDD have reached the respective threshold voltages. The shutdown thresholds for the supply voltages can be adjusted as shown in Equation 1 and Equation 2. The supervisor can also be removed from the shutdown logic by depopulating R5. For more information on the reset supervisor, see the TPS37xx Dual-Channel, Low-Power, High-Accuracy Voltage Detectors data sheet.

Equation 1. V M O N ( A V D D ) = 1 + R 3 R 4 × 1.188
Equation 2. V M O N ( I O V D D ) = 1 + R 1 R 2 × 1.188