SBAU462 June   2024 PCM1809

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Power Supply
    2. 2.2 Hardware Configuration
    3. 2.3 PCM1809EVM Inputs
      1. 2.3.1 Onboard Microphone Inputs
      2. 2.3.2 Line Inputs
  7. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 Layer Plots
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1. 4.1 Trademarks

2.2 Hardware Configuration

The format of the audio data and the operating mode of the ADC are controlled by the following pins: MD0,MD1, MSZ, and FMT0. These signals are referenced to IOVDD and can be set to high (1) or low (0). If no shunt is installed, then a 47kΩ pulldown resistor sets the pin low so that the ADC remains in a defined state. Table 3-1 shows the header numbers and the pin functions and Table 3-2, Table 3-2 and , Table 3-2 show the possible modes and output formats. The MSZ pin selects whether the device is a controller or a target on the audio bus. When MSZ is pulled high, the device is in controller mode and MD1 becomes an input for MCLK. A shunt connecting J19 to the center pin of J18 routes the MCLK signal provided on J8 to the MD1 pin on the ADC to allow for easy interfacing with audio measurement equipment.

Table 2-1 PCM1809EVM Headers and Jumpers
DesignatorFunction
J1Differential line/mic input 1
J2Differential line/mic input 2
J4MICBIAS Selection
J5IOVDD-SYS voltage Selection (1.8V or 3.3V)
J6+5V input
J7AC-MB Connector
J8Audio Serial Interface header
J9Connect AVDD to onboard 3.3V regulator
J10Connect IOVDD to onboard regulator
J11Connect MICBIAS to onboard MIC2
J12Connect MIC2 OUT+ to ADC IN2P
J13MSZ select
J14Connect MICBIAS to onboard MIC1
J15Connect MIC1 OUT+ to ADC IN1P
J16Connect MIC1 OUT- to ADC IN1M
J17MD0 select
J18MD1 select
J19MCLK to MD1
J20FMT0 select
J21Connect MIC2 OUT- to ADC IN2M
J22IN2M capacitor bypass
J23IN1P capacitor bypass
J24IN2P capacitor bypass
J25IN1M capacitor bypass
Table 2-2 PCM1809EVM Modes
MD0 Modes
MD0MSZ (0 = Target, 1 = Controller)MD0 Functional Mode
00Linear phase filters are used for the decimation in target mode. For controller mode, the device always use linear phase filters for the decimation.
01System clock with frequency 256 × fS connected to the MD1 pin as MCLK.
10System clock with frequency 512 × fS connected to the MD1 pin as MCLK.
11Low latency filters are used for the decimation in target mode. For controller mode, the device always use linear phase filters for the decimation.
Table 2-3 PCM1809EVM MD1 Modes
MD1 Modes
MD1MSZ (0 = Target, 1 = Controller)Functional mode
X0Target mode
MCLK1MCLK input in controller mode
Table 2-4 PCM1809EVM Audio Output Format
Audio Output Data Format
FMT0Audio Serial Interface Format
02-channel output with inter IC sound (I2S) mode
12-channel output with time division multiplexing (TDM) mode

All hardware pins are tied low by default, placing the device in target mode with a linear phase filter and 2-channel I2S audio output. For more information on the operating modes of the PCM1809 device, see the PCM1809 Stereo Channel, 102dB Dynamic Range Audio ADC data sheet.