SBOS729A October   2015  – March 2016 DRV425

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fluxgate Sensor Front-End
        1. 7.3.1.1 Fluxgate Sensor
        2. 7.3.1.2 Bandwidth
        3. 7.3.1.3 Differential Driver for the Internal Compensation Coil
        4. 7.3.1.4 Magnetic Field Range, Overrange Indicator, and Error Flag
      2. 7.3.2 Shunt-Sense Amplifier
      3. 7.3.3 Voltage Reference
      4. 7.3.4 Low-Power Operation of the DRV425
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Linear Position Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Current Sensing in Busbars
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 Power-Supply Decoupling
    2. 9.2 Power-On Start-Up and Brownout
    3. 9.3 Power Dissipation
      1. 9.3.1 Thermal Pad
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RTJ Package
20-Pin WQFN
Top View
DRV425 po_bos729.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AINN 14 I Inverting input of the shunt-sense amplifier
AINP 13 I Noninverting input of the shunt-sense amplifier
BSEL 1 I Filter bandwidth select input
COMP1 16 I Internal compensation coil input 1
COMP2 17 I Internal compensation coil input 2
DRV1 12 O Compensation coil driver output 1
DRV2 11 O Compensation coil driver output 2
ERROR 19 O Error flag: open-drain, active-low output
GND 7, 10, 18, 20 — Ground reference
OR 15 O Shunt-sense amplifier overrange indicator: open-drain, active-low output
PowerPAD — Connect the thermal pad to GND
REFIN 5 I Common-mode reference input for the shunt-sense amplifier
REFOUT 4 O Voltage reference output
RSEL0 3 I Voltage reference mode selection input 0
RSEL1 2 I Voltage reference mode selection input 1
VDD 8, 9 — Supply voltage, 3.0 V to 5.5 V. Decouple both pins using 1-µF ceramic capacitors placed as close as possible to the device. See the Power-Supply Decoupling and Layout sections for further details.
VOUT 6 O Shunt-sense amplifier output