SBOS853B March   2017  – December 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements #GUID-D86987F5-A9B7-4506-9858-90867D8ED8B3/SBOS6814062
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Human Eye Matching
      2. 6.3.2 Automatic Full-Scale Range Setting
      3. 6.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 6.3.4 I2C Bus Overview
        1. 6.3.4.1 Serial Bus Address
        2. 6.3.4.2 Serial Interface
    4. 6.4 Device Functional Modes
      1. 6.4.1 Automatic Full-Scale Setting Mode
      2. 6.4.2 Interrupt Reporting Mechanism Modes
        1. 6.4.2.1 Latched Window-Style Comparison Mode
        2. 6.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 6.4.2.3 End-of-Conversion Mode
        4. 6.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 6.5 Programming
      1. 6.5.1 Writing and Reading
        1. 6.5.1.1 High-Speed I2C Mode
        2. 6.5.1.2 General-Call Reset Command
        3. 6.5.1.3 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Internal Registers
      1. 7.1.1 Register Descriptions
        1. 7.1.1.1 Result Register (offset = 00h)
        2. 7.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
        3. 7.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
        4. 7.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
        5. 7.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
        6. 7.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Optomechanical Design
        2. 8.2.2.2 Dark Window Selection and Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Soldering and Handling Recommendations
    2. 11.2 DNP (S-PDSO-N6) Mechanical Drawings
    3. 11.3 DTS (SOT-5X3) Mechanical Drawings

6.4.2.3 End-of-Conversion Mode

An end-of-conversion indicator mode can be used when every measurement is desired to be read by the processor, prompted by the INT pin going active on every measurement completion. This mode is entered by setting the most significant two bits of the low-limit register (LE[3:2] from the Low-Limit Register) to 11b. This end-of-conversion mode is typically used in conjunction with the latched window-style comparison mode. The INT pin becomes inactive when the configuration register is read or the configuration register is written with a non-shutdown parameter or in response to an SMBus alert response. Table 6-4 summarizes the interrupt reporting mechanisms as a result of various operations.

Table 6-4 End-of-Conversion Mode while in Latched Window-Style Comparison Mode:
Flag Setting and Clearing Summary(1)
OPERATIONFLAG HIGH FIELDFLAG LOW FIELDINT PIN(1)CONVERSION READY FIELD
The result register is above the high-limit register for fault count times. See the Result Register and the High-Limit Register for further details.1XActive1
The result register is below the low-limit register for fault count times. See the Result Register and the Low-Limit Register for further details.X1Active1
The conversion is complete with fault count criterion not metXXActive1
Configuration register read(1)00Inactive0
Configuration register write, M[1:0] = 00b (shutdown)XXXX
Configuration register write, M[1:0] > 00b (not shutdown)XXX0
SMBus alert response protocolXXInactiveX

Note that when transitioning from end-of-conversion mode to the standard comparison modes (that is, programming LE[3:2] from 11b to 00b) while the configuration register latch field (L) is 1, a subsequent write to the configuration register latch field (L) to 0 is necessary to properly clear the INT pin. The latch field can then be set back to 1 if desired.