SBOU315 March   2024 PGA849

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 EVM Circuit Description
    2. 2.2 Jumper Settings
    3. 2.3 Power-Supply Connections
    4. 2.4 Analog Input and Output Connections
    5. 2.5 Reference Input
    6. 2.6 Digital Input Pins and Gain Control
    7. 2.7 Modifications
    8. 2.8 Best Practices
      1. 2.8.1 Electrostatic Discharge Caution
      2. 2.8.2 Hot Surface Warning
  8. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5Related Documentation

Power-Supply Connections

The PGA849EVM uses two sets of voltage supplies: input stage and output stage. The device operates using input-stage power supplies from ±4V (8V) to ±18V (36V) and output-stage power supplies from ±2.25V (4.5V) to ±18V (36V). The output-stage supply voltage must not exceed the input-stage supply voltage.

The input-stage power-supply connections for the PGA849EVM are provided through connector J13 at the top of the EVM. The input-stage positive power-supply connection is labeled +VCC, the negative power-supply connection is labeled –VEE, and the ground connection is labeled GND. To connect power to the PGA849EVM, insert wires into each terminal of J13 and then tighten the screws to make the connection. Table 3-4 summarizes the pin definition for supply connector J1 and the allowed voltage range for each supply connection.

Table 2-2 PGA849EVM Supply-Range Specifications
Connector Pin Number Supply Connection Voltage Range
J13.3 Input-stage positive supply (+VCC) Single supply, VS = +VCC: 8V to 36V
Dual supply, VS = (+VCC) – (–VEE): 4V to 18V
J13.2 Ground 0V
J13.1 Negative supply (–VEE) Single supply, VS = +VCC: 0V (GND)
Dual supply, VS = (+VCC) – (–VEE): –4 V to –18 V
J14.1

LVDD+_ext

Single supply, LVDD+_ext: 4.5V to 36V
Dual supply, output stage supply (LVSS+) – (LVSS–): 2.25V to 18V
J14.2 Ground 0V
J14.3 LVSS–_ext Single supply, LVSS–_ext: 0V (GND)
Dual supply, output stage supply (LVSS+) – (LVSS–): –2.25V to –18V
J14.4 Ground 0V

By default, the output-stage supply-voltage levels (+LVDD and –LVSS) are set to the PGA849 positive (+VCC) and negative (–VEE) supplies, respectively. The +LVDD pin is connected to +VCC through jumper J9 1-2, and the –LVSS pin is connected to –VEE through J16 1-2. Screw terminal connector J14 provides access to the output-stage supply pins. To set the voltage level of LVDD and LVSS with an external supply, shunt jumper J9 2-3 to access the +LVDD using connector J14.1. In a similar fashion, shunt jumper J16 2-3 to access the –LVSS pin using connector J14.3.

Figure 3-3 shows the PGA849EVM voltage supply connections.

GUID-20240311-SS0I-RHRT-G9DF-KSSHD1K3PJ7N-low.svgFigure 2-3 PGA849EVM Voltage Supply Connections