Design Flexibility of TPS7A1408 to Variable Vout and Stability Check
Abstract
TPS7A14 is a small, ultra low-dropout regulator with excellent transient response and can provide sourcing current up to 1-A peak. Normally, key design performance of LDO includes high PSRR, low noise, low ripple, fast transient response, low quiescent at no load condition, good line and load regulation. And also, the stability is always necessary for LDO. TPS7A14 specifies these requirements superior and can be useful for the application of low input and low dropout power rails. It features NMOS pass element and fixed Vout so for optimized package and schematic size. This application note addresses the flexibility to adjustable Vout configuration and followed concerns on loop stability.
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1 Introduction
TPS7A14xx is available for a wide range of output voltages but in fixed steps of 25 mV, and it is changeable through OTP process. However, in some applications, applying multiple TPS7A14 for variable power rails, there is a need to have them unified for design flexibility as well as management matters. Starting from understanding of inside blocks, users can easily configure adjustable Vout rails
1.1 TPS7A14 Functional Block Diagram
Figure 1-1 shows how internal circuitry is connected and its functional blocks. Generally, NMOSFET pass transistor has low impedance at output stage. Hence it can provide low noise performance since NMOS LDO has a low spike/ripple at output which is dependent on output impedance. Unit gain Opamp named as EA (error amplifier) monitors output voltage directly via SENSE pin and its reference_Vref at non-inverting input comes from the additional Op amp loop. It has a dedicated gain to make Vref follow desired Vout in 25-mV steps and it can be trimmed through OTP process adjusting RB of its resistor network. Bandgap 1.2 V is supplied from external biasing accommodating ultra low dropout at low output voltages. Section 1.2 will address the reason why NMOS LDO needs external biasing.
1.2 Biasing Rail for NMOS LDO
LDO, especially pass element(dealing MOSFET only here) works in the linear region to reduce the input voltage down to the required output voltage and it is controlled by error amplifier changing FET’s gate to the appropriate operating point at a given load condition, or accordingly when the input voltage changes. Key note is that the pass element behaves like a simple resistor. We understand drain-to-source resistance Rds is moving its value inside linear region area of MOSFET. If we consider only pass element, conventional background says that N-type power stage has higher dropout limitation than that of P-type and it’s true that because error amplifier will saturate at the input supply voltage as Vin approached to Vout. Figure 1-2 illustrates the mechanism.
Figure 1-2 Dropout Limitation of NMOS LDO As Vin approaches Vout, error amplifier compensates it through lowering the Rds in order to maintain regulation. However, since the collapsing Vin supplies the amplifier VGS cannot be more positively increased at a certain point. It results in unregulated Vout. Limited Rds multiplied by output load current will derive more dropout from nominal Vout. That’s because there are two options to overcome this challenge. One is to have external biasing for gate driving and the other one is a charge pump.
Figure 1-3 NMOS LDO with an External BiasingVBIAS serves as the positive supply rail for error amplifier and allows its output to swing up to VBIAS. Now though Vin approaches Vout, driver circuit enables maintaining a high VGS. This makes Rds lower achieving ultra low dropout performance. Note that minimum bias voltage above the nominal desired Vout must be maintained. The information about minimum VBIAS headroom is provided commonly in the product data sheet.
