SBVA102 august   2023 TPS56837

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2D-CAP3 Control Architecture
    1. 2.1 Adaptive On-Time Control
    2. 2.2 D-CAP3 Control
  6. 3Large Duty Cycle Operation
    1. 3.1 Min Off-Time Performance of Buck Converters
    2. 3.2 On-Time Extension Function
  7. 4Bench Test and Comparison
    1. 4.1 Comparison Between TPS56837 and TPS56637
    2. 4.2 Comparison of On-Time Extension between TPS56837 and TPS568230
    3. 4.3 Load Transient Improvement by On-Time Extension
  8. 5Summary
  9. 6References
  10. 7Also From TI

2.2 D-CAP3 Control

Figure 2-2 shows the detailed control block diagram of D-CAP3™ converters.

GUID-20230820-SS0I-B1HK-HFPG-LJTVNW9TQWKP-low.svgFigure 2-2 Detail D-CAP3 Control Block Diagram

To improve loop stability with virtually no ripple on the output voltage, an additional ripple injection circuit is added. Also an included error amplifier improves the output voltage accuracy.

In the control block of the D-CAP3™ device, the boot capacitor needs to be charged during low-side MOSFET on, in the meanwhile, the inductor valley current is monitored by measuring the SW node voltage during this off-time, which both lead a minimum off time requirement.

As we know, most of the High-side MOSFETs are N-MOS and need a voltage higher than Vin for Gate driver to keep the High-side MOS on, and the voltage is provided by BOOT capacitor. This capacitor is charged during off-time, thus the off-time has a minimum value to ensure the charges of BOOT capacitor are enough.

For D-CAP3™ converters, when the one-shot timer is expired, the high-side MOSFET is turned off and the low-side MOSFET is turned on. The turning on process of the low-side MOSFET causes the SW ringing. When measuring the SW node voltage, a blanking time needs to be included to let the internal SW node ringing dissipate. This time delay results in the minimum off time for the high-side MOSFET.