SBVU069
February 2021
TPS785-Q1
Trademarks
1
Introduction
1.1
Before You Begin
2
EVM Setup
2.1
Input/Output Connector and Jumper Descriptions
2.1.1
J1 – VIN (Banana Jack)
2.1.2
J2 – VOUT (Banana Jack)
2.1.3
J3 – VIN_S
2.1.4
J4 – VOUT_S
2.1.5
J5 – VEN
2.1.6
J6 – GND (Banana Jack)
2.1.7
J7 – GND (Banana Jack)
2.1.8
J8 – OUTPUT VOLTAGE SET
2.1.9
J9 – VIN (TERMINAL BLOCK)
2.1.10
J10 – VOUT (TERMINAL BLOCK)
2.1.11
J11 – DEBUG TERMINAL
2.1.12
TP1 – VIN_S
2.1.13
TP2 – VOUT_S
2.1.14
TP3 – VEN
2.1.15
TP4 – TP6 – GND
3
Soldering Guidelines
4
Equipment Connection
5
Operation
6
PCB Layout
7
Schematic
8
Bill of Materials
6
PCB Layout
Figure 6-1
to
Figure 6-5
illustrate the PCB layout for this EVM.
Figure 6-1
Top Composite View
Figure 6-3
Signal Layer 1 Routing
Figure 6-5
Bottom Layer Routing
Figure 6-2
Top Layer Routing
Figure 6-4
Signal Layer 2 Routing