SBVU069 February   2021 TPS785-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2EVM Setup
    1. 2.1 Input/Output Connector and Jumper Descriptions
      1. 2.1.1  J1 – VIN (Banana Jack)
      2. 2.1.2  J2 – VOUT (Banana Jack)
      3. 2.1.3  J3 – VIN_S
      4. 2.1.4  J4 – VOUT_S
      5. 2.1.5  J5 – VEN
      6. 2.1.6  J6 – GND (Banana Jack)
      7. 2.1.7  J7 – GND (Banana Jack)
      8. 2.1.8  J8 – OUTPUT VOLTAGE SET
      9. 2.1.9  J9 – VIN (TERMINAL BLOCK)
      10. 2.1.10 J10 – VOUT (TERMINAL BLOCK)
      11. 2.1.11 J11 – DEBUG TERMINAL
      12. 2.1.12 TP1 – VIN_S
      13. 2.1.13 TP2 – VOUT_S
      14. 2.1.14 TP3 – VEN
      15. 2.1.15 TP4 – TP6 – GND
  4. 3Soldering Guidelines
  5. 4Equipment Connection
  6. 5Operation
  7. 6PCB Layout
  8. 7Schematic
  9. 8Bill of Materials

PCB Layout

Figure 6-1 to Figure 6-5 illustrate the PCB layout for this EVM.

GUID-20210122-CA0I-H72T-QJ7J-KSDRMTP4MX2T-low.svgFigure 6-1 Top Composite View
GUID-20210122-CA0I-MBVT-F240-K6FV16GVZCG1-low.svgFigure 6-3 Signal Layer 1 Routing
GUID-20210122-CA0I-WQML-FGG9-C0DLVHVZRB6T-low.svgFigure 6-5 Bottom Layer Routing
GUID-20210122-CA0I-FDLW-PMDW-0MCPVJBV3R1L-low.svgFigure 6-2 Top Layer Routing
GUID-20210122-CA0I-9NGC-HBHZ-K0HRNLFCLTD3-low.svgFigure 6-4 Signal Layer 2 Routing