SCDA008C June   2021  – November 2021 CD4052B , TS3A225E , TS3A44159

 

  1.   Trademarks
  2. 1Introduction
  3. 2Semiconductor Switches
    1. 2.1 NMOS Switch
    2. 2.2 PMOS Switch
  4. 3Basic Signal-Switch Structures
    1. 3.1 NMOS Series Switch
    2. 3.2 NMOS/PMOS Parallel Switch
    3. 3.3 NMOS Series Switch with the Charge Pump
  5. 4Key Concerns in Digital-Switch Applications
    1. 4.1  Power and Control Voltage Requirements
    2. 4.2  Rail-to-Rail Operation
    3. 4.3  Undershoot
    4. 4.4  ron
    5. 4.5  Cio(off)
    6. 4.6  Cio(on)
    7. 4.7  Ci (Control Input Capacitance)
    8. 4.8  Leakage Current
    9. 4.9  Enable and Disable Delays and Propagation Delay
    10. 4.10 Partial Power Down
    11. 4.11 Voltage Translation
  6. 5Signal Switch Families
    1. 5.1 CBT-C Family
      1. 5.1.1 Characteristics of CBT-C Family
        1. 5.1.1.1 VOvs VI
        2. 5.1.1.2 ron vs VI
        3. 5.1.1.3 Undershoot Protection
      2. 5.1.2 Application of CBT-C Family
        1. 5.1.2.1 Bus Isolation
    2. 5.2 CBTLV Family
      1. 5.2.1 Characteristics of the CBTLV Family
    3. 5.3 CB3Q Family
      1. 5.3.1 Characteristics of the CB3Q Family
        1. 5.3.1.1 VOvs VI
        2. 5.3.1.2 ron vs VI
        3. 5.3.1.3 Operation at High Frequency
        4. 5.3.1.4 Output Skew
        5. 5.3.1.5 Frequency Response
        6. 5.3.1.6 Adjacent Channel Crosstalk
      2. 5.3.2 Application of the CB3Q Family
        1. 5.3.2.1 Multiplexer in USB Applications
    4. 5.4 CB3T Family
      1. 5.4.1 Characteristics of the CB3T Family
        1. 5.4.1.1 VO vs VI
        2. 5.4.1.2 ron vs VI
        3. 5.4.1.3 Operation at High Frequency
      2. 5.4.2 Application of the CB3T Family
        1. 5.4.2.1 Voltage Translation for an External Monitor Terminal in a Notebook PC
  7. 6Applications
    1. 6.1 Multiplexing USB Peripherals
    2. 6.2 Multiplexing Ethernet
    3. 6.3 Notebook Docking Station
  8. 7Conclusion
  9. 8References
  10. 9Revision History
  11.   A Test Measurement Circuits
    1.     A.1 Measurement Setup for ron
    2.     A.2 Measurement Setup for VO vs VI Characteristics
    3.     A.3 Voltage-Time Waveform Measurement (Switch On)
    4.     A.4 Voltage-Time Waveform Measurement (Switch Off)
    5.     A.5 Output-Skew Measurement
    6.     A.6 Simulation Setup for Undershoot Measurement
    7.     A.7 Laboratory Setup for Attenuation Measurement
    8.     A.8 Laboratory Setup for Off Isolation Measurement
    9.     A.9 Laboratory Setup for Crosstalk Measurement

4.3 Undershoot

Undershoot is a typical phenomenon in high-speed applications where impedance mismatches cause excessive ringing in the system. This poses a serious problem to bus switches that are turned off and attempt to isolate different buses. In this state, the gate voltage of the n-channel pass transistors are at ground potential, but a negative voltage on either I/O port with a magnitude greater than the NMOS VT will cause the switch to conduct and no longer isolate the buses. Therefore, undershoots with a large magnitude and long duration result in data corruption, if no undershoot protection circuitry is included in the signal-switch design. The schematics in Figure 4-3 demonstrate the phenomenon of undershoots. For normal input voltages ranging from 0 V to VCC, the switch is in the high-impedance state and the output bus is isolated from the input bus. The undershoot produces a glitch at the isolated bus, as shown in Figure 4-3.

GUID-96122BC4-7AF3-42F3-946C-F7A5616F570C-low.gifFigure 4-3 Undershoot in NMOS Series-Switch Devices When Disabled

There are two solutions to prevent the NMOS from turning on during the undershoot even while disabled:

  • Capture or clamp the input undershoot energy. In this method, a clamp circuit is connected to ground or VCC. This clamp circuit prevents the NMOS from turning on while an undershoot event occurs.
    • Schottky Clamp. In this method, a Schottky diode is connected from the I/O port of the switch to ground. When the voltage at the I/O port goes below ground, the diode is forward biased and clamps the source or drain voltage, keeping the input and output isolated. An example of this type of device is the CBTS bus switch provided by TI.
    • Active clamp to VCC. In this method, an active clamp circuit is connected to VCC, which tries to counteract the undershoot voltage by pulling the input voltage to VCC. An example of this type of device is the CBTK bus switch provided by TI.
  • Force the gate voltage of the NMOS to track the negative input voltage. TI’s new CBT-C family uses this method to prevent undershoot. This method of protection is described later in this application report.