4 Using Lookup Tables to Reduce Schematic

Figure 4-1 is an example of a bus arbitration logic. The purpose of this logic is to determine which controller has priority on the bus at any given time. If both RX are low the buses are being held high. Each color box represents a different physical device. Table 4-1 shows the total area of this design upon discrete implementation without even accounting for tolerances between devices or traces needed to interconnect the devices.

By looking at the inputs to certain groupings of logic gates we can separate this design into 4 groups. Each one of these groups can be simplified down into a single LUT as shown in Figure 4-2.

Now that the schematic has been separated as such we can bring this design into ICS we can create a configuration with 4 pins and 4 LUTs to complete this schematic as shown in Figure 4-3.The configuration of lut1 is 2 input with the table shown in Table 4-2. The configuration of lut2 and lut3 are 3 input with the table shown in Table 4-4. the configuration of lut4 is 2 input with the table shown in Table 4-3.