Agile I/O’s offer programmable output drive strength that allows the I/O pad to be configured to one of four possible current levels. By programming the bits in the Output Drive Strength Registers, the user can adjust the number of transistor pairs that drive the I/O pad. Table 2-1 is from the TCAL6416 data sheet and describes registers 40, 41, 42, and 43 (Output Drive Strength Registers).

Each P-port is assigned exactly 2 bits to configure the drive strength of the output driver. For example, P07 (which is the port 0 GPIO 7) output is configured by two bits located in register 41 called CC-07. Two configurable bits presents four different output current level options which are defined in Table 2-2. The default drive strength for an output pin is 1.00x (CC = 11).

The configurable bits for CC-XX determines the number of transistor pairs that are ON at a given time that feed the I/O pad. Figure 2-1 shows the PMOS/NMOS_EN devices that control the push-pull driving pairs that output on P00 – P07 and P10 – P17. Figure 2-1 is a simplified output stage of the p-port.

Figure 2-1 Simplified Output Stage

Reducing output drive strength has a few benefits:

• Weaker outputs slow down the slew rate reducing ringing effects.
• Different pins can have different loading conditions, some can require using the full drive strength while others need weaker drive strength. Thus, each pin can be configured separately where some need the original full drive strength configuration.
• Reduces overall power consumption.

Agile I/O’s offer programmable internal pull-up or pull-down resistors accessed by register addressing. The user has the ability to internally connect a weak pull-up or pull-down resistor (approximately 100 kΩ) onto the p-port pad. Figure 3-1 is a functional diagram that shows the internal connection and control block for programmable pull-up or pull-down resistors. Pull-up or pull-down resistors are disabled when the p-port is configured as an output.

Figure 3-1 Pull-Up or Pull-Down Control Path to P-Ports

Latchable inputs are useful when the user wants to maintain that an interrupt is not lost during an input’s transition back to the original state. With latchable inputs disabled, a state change in the corresponding input pin generates an interrupt on /INT, and stores the input logic value into the corresponding bit of the input port register (registers 0 and 1). A read of the input register clears the interrupt flag. If the input goes back to the initial logic state before the input port register is read, then the interrupt flag on /INT clears itself which can cause issues because an interrupt can be lost if not read before the input state changes.

This behavior can be observed in the scope capture in Figure 4-1. Input P04 on the TCAL6416 is driven from a high to low logic state. After some time passes, the input is driven back to high. Note that the interrupt that was asserted to low goes back to high once the original input state on P04 is achieved. In this case, the interrupt is lost.

Figure 4-1 Interrupt is Asserted and Lost Due to Input Un-Latched

This situation changes when the latchable input is enabled. A change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0 and 1). A read of the input port register clears the interrupt flag on /INT. In this case, if the input port register is read after the input pin returns to the initial logic state, the interrupt flag on /INT does not clear, and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. This process maintains that no triggered interrupt is lost due to a transition back to original state on the input pin. This behavior can be observed in the scope capture in Figure 4-2.

Figure 4-2 Interrupt is Asserted and Kept Due to Input Latched

This behavior is a key difference between TCA devices and TCAL devices concerning the latchable input feature of Agile I/O’s.